DE60031214D1 - Spannungsschutzschaltung und -Verfahren für einen Eingangs/Ausgangsanschluss - Google Patents

Spannungsschutzschaltung und -Verfahren für einen Eingangs/Ausgangsanschluss

Info

Publication number
DE60031214D1
DE60031214D1 DE60031214T DE60031214T DE60031214D1 DE 60031214 D1 DE60031214 D1 DE 60031214D1 DE 60031214 T DE60031214 T DE 60031214T DE 60031214 T DE60031214 T DE 60031214T DE 60031214 D1 DE60031214 D1 DE 60031214D1
Authority
DE
Germany
Prior art keywords
input
output port
protection circuit
voltage protection
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60031214T
Other languages
English (en)
Other versions
DE60031214T2 (de
Inventor
Oleg Drapkin
Grigori Temkine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Original Assignee
ATI International SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI International SRL filed Critical ATI International SRL
Publication of DE60031214D1 publication Critical patent/DE60031214D1/de
Application granted granted Critical
Publication of DE60031214T2 publication Critical patent/DE60031214T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE60031214T 1999-09-02 2000-08-31 Spannungsschutzschaltung und -Verfahren für einen Eingangs/Ausgangsanschluss Expired - Lifetime DE60031214T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US388988 1999-09-02
US09/388,988 US6400546B1 (en) 1999-09-02 1999-09-02 I/O pad voltage protection circuit and method

Publications (2)

Publication Number Publication Date
DE60031214D1 true DE60031214D1 (de) 2006-11-23
DE60031214T2 DE60031214T2 (de) 2007-08-23

Family

ID=23536384

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60031214T Expired - Lifetime DE60031214T2 (de) 1999-09-02 2000-08-31 Spannungsschutzschaltung und -Verfahren für einen Eingangs/Ausgangsanschluss

Country Status (3)

Country Link
US (1) US6400546B1 (de)
EP (1) EP1081859B1 (de)
DE (1) DE60031214T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694444B1 (en) * 2000-06-30 2004-02-17 Intel Corporation System and method for reducing over-shoot and ringback by delaying input and establishing a synchronized pulse over which clamping is applied
DE10040092A1 (de) * 2000-08-16 2002-03-07 Infineon Technologies Ag Schaltungsanordnung zur Erkennung eines Fehlerzustands
US6785828B2 (en) * 2000-12-20 2004-08-31 Intel Corporation Apparatus and method for a low power, multi-level GTL I/O buffer with fast restoration of static bias
US6798629B1 (en) * 2001-06-15 2004-09-28 Integrated Device Technology, Inc. Overvoltage protection circuits that utilize capacitively bootstrapped variable voltages
JP4043855B2 (ja) * 2002-06-10 2008-02-06 株式会社日立製作所 半導体集積回路装置
US6624682B1 (en) * 2002-10-09 2003-09-23 Analog Devices, Inc. Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage
US20050035806A1 (en) * 2003-07-24 2005-02-17 El-Sherif Alaa Y. Circuit and method to protect EEPROM data during ESD events
US7133269B2 (en) * 2004-03-04 2006-11-07 Via Technologies, Inc. Overvoltage protection apparatus
CN1947253A (zh) * 2004-04-09 2007-04-11 株式会社半导体能源研究所 限幅器以及采用限幅器的半导体器件
US7274544B2 (en) * 2004-10-21 2007-09-25 Taiwan Semiconductor Manufacturing Company Gate-coupled ESD protection circuit for high voltage tolerant I/O
US7227376B2 (en) * 2004-11-05 2007-06-05 Ati Technologies Inc. Dynamic impedance compensation circuit and method
US7649400B2 (en) * 2005-09-28 2010-01-19 Texas Instruments Incorporated Back gate biasing overshoot and undershoot protection circuitry
US7345510B1 (en) * 2006-08-31 2008-03-18 Ati Technologies Inc. Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal
ITMI20062237A1 (it) * 2006-11-22 2008-05-23 St Microelectronics Srl Circuito elettrico con protezione dalle sovratensioni
TW201226950A (en) * 2006-12-27 2012-07-01 Hynix Semiconductor Inc Semiconductor device and its testing method
US7835124B2 (en) * 2007-01-02 2010-11-16 Freescale Semiconductor, Inc. Short circuit and over-voltage protection for a data bus
WO2009046013A1 (en) * 2007-10-01 2009-04-09 Maxim Integrated Products, Inc. Input voltage clamp for a single-supply system
US8344760B2 (en) * 2008-07-17 2013-01-01 Ati Technologies Ulc Input/output buffer circuit
US8238067B2 (en) * 2008-12-11 2012-08-07 Ati Technologies Ulc Electrostatic discharge circuit and method
US8947839B2 (en) * 2009-07-30 2015-02-03 Xilinx, Inc. Enhanced immunity from electrostatic discharge
US8456784B2 (en) * 2010-05-03 2013-06-04 Freescale Semiconductor, Inc. Overvoltage protection circuit for an integrated circuit
CN102522950B (zh) 2012-01-06 2015-04-29 开曼群岛威睿电通股份有限公司 具有输出信号转换率控制的电子芯片
US9438030B2 (en) 2012-11-20 2016-09-06 Freescale Semiconductor, Inc. Trigger circuit and method for improved transient immunity
US9088274B1 (en) * 2014-01-26 2015-07-21 Freescale Semiconductor, Inc. Voltage clamping circuit
CN110855277B (zh) * 2019-12-02 2021-07-23 思瑞浦微电子科技（苏州）股份有限公司 可调钳位电路
US11531363B2 (en) * 2020-01-06 2022-12-20 Arm Limited Voltage tracking circuitry for output pad voltage
TWI733630B (zh) * 2020-12-07 2021-07-11 智原科技股份有限公司 輸出入模組

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534811A (en) 1993-06-18 1996-07-09 Digital Equipment Corporation Integrated I/O bus circuit protection for multiple-driven system bus signals
US5473500A (en) 1994-01-13 1995-12-05 Atmel Corporation Electrostatic discharge circuit for high speed, high voltage circuitry
US5923202A (en) * 1997-03-03 1999-07-13 National Semiconductor Corporation Input/output overvoltage containment circuit for improved latchup protection
AU7367698A (en) * 1997-05-07 1998-11-27 California Micro Devices Corporation Active termination circuit and method therefor
US5852540A (en) * 1997-09-24 1998-12-22 Intel Corporation Circuit for protecting the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels
US6049445A (en) * 1998-09-18 2000-04-11 International Business Machines Corporation Overvoltage and electrostatic discharge protection for a receiver circuit

Also Published As

Publication number Publication date
EP1081859A1 (de) 2001-03-07
EP1081859B1 (de) 2006-10-11
US6400546B1 (en) 2002-06-04
DE60031214T2 (de) 2007-08-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ATI TECHNOLOGIES ULC, CALGARY, ALBERTA, CA

8328 Change in the person/name/address of the agent

Representative=s name: MARKS & CLERK (LUXEMBOURG) LLP, LUXEMBOURG, LU