DE60026178D1 - Modellierung und prüfung einer integrierten schaltung - Google Patents
Modellierung und prüfung einer integrierten schaltungInfo
- Publication number
- DE60026178D1 DE60026178D1 DE60026178T DE60026178T DE60026178D1 DE 60026178 D1 DE60026178 D1 DE 60026178D1 DE 60026178 T DE60026178 T DE 60026178T DE 60026178 T DE60026178 T DE 60026178T DE 60026178 D1 DE60026178 D1 DE 60026178D1
- Authority
- DE
- Germany
- Prior art keywords
- modeling
- inspection
- integrated circuit
- integrated
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/460,254 US6546514B1 (en) | 1999-12-13 | 1999-12-13 | Integrated circuit analysis and design involving defective circuit element replacement on a netlist |
US460254 | 1999-12-13 | ||
PCT/US2000/042680 WO2001045565A2 (en) | 1999-12-13 | 2000-12-07 | Modeling and testing of an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60026178D1 true DE60026178D1 (de) | 2006-04-27 |
DE60026178T2 DE60026178T2 (de) | 2006-11-09 |
Family
ID=23827962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60026178T Expired - Lifetime DE60026178T2 (de) | 1999-12-13 | 2000-12-07 | Modellierung und prüfung einer integrierten schaltung |
Country Status (5)
Country | Link |
---|---|
US (1) | US6546514B1 (de) |
EP (1) | EP1259165B1 (de) |
JP (1) | JP2003523001A (de) |
DE (1) | DE60026178T2 (de) |
WO (1) | WO2001045565A2 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001201543A (ja) * | 2000-01-18 | 2001-07-27 | Rooran:Kk | スキャン・パス構築用プログラムを記録した記録媒体とスキャン・パスの構築方法及びこのスキャン・パスを組み込んだ演算処理システム |
US20040098646A1 (en) * | 2002-11-20 | 2004-05-20 | Fisher Rory L. | Method and apparatus to check the integrity of scan chain connectivity by traversing the test logic of the device |
US7194706B2 (en) * | 2004-07-27 | 2007-03-20 | International Business Machines Corporation | Designing scan chains with specific parameter sensitivities to identify process defects |
US20070011544A1 (en) * | 2005-06-15 | 2007-01-11 | Hsiu-Huan Shen | Reprogramming of tester resource assignments |
US9310433B2 (en) | 2014-04-18 | 2016-04-12 | Breker Verification Systems | Testing SOC with portable scenario models and at different levels |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS647400A (en) * | 1987-06-29 | 1989-01-11 | Hitachi Ltd | Ic tester |
US5111413A (en) * | 1989-03-24 | 1992-05-05 | Vantage Analysis Systems, Inc. | Computer-aided engineering |
US5629860A (en) * | 1994-05-16 | 1997-05-13 | Motorola, Inc. | Method for determining timing delays associated with placement and routing of an integrated circuit |
US5754826A (en) * | 1995-08-04 | 1998-05-19 | Synopsys, Inc. | CAD and simulation system for targeting IC designs to multiple fabrication processes |
US5938782A (en) | 1996-09-24 | 1999-08-17 | Vlsi Technology, Inc. | Scan flip-flop and methods for controlling the entry of data therein |
US6219813B1 (en) * | 1998-06-29 | 2001-04-17 | International Business Machines Corporation | Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip |
US6308309B1 (en) * | 1999-08-13 | 2001-10-23 | Xilinx, Inc. | Place-holding library elements for defining routing paths |
-
1999
- 1999-12-13 US US09/460,254 patent/US6546514B1/en not_active Expired - Fee Related
-
2000
- 2000-12-07 JP JP2001546307A patent/JP2003523001A/ja not_active Withdrawn
- 2000-12-07 DE DE60026178T patent/DE60026178T2/de not_active Expired - Lifetime
- 2000-12-07 EP EP00992873A patent/EP1259165B1/de not_active Expired - Lifetime
- 2000-12-07 WO PCT/US2000/042680 patent/WO2001045565A2/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP1259165A2 (de) | 2002-11-27 |
WO2001045565A3 (en) | 2002-09-12 |
JP2003523001A (ja) | 2003-07-29 |
DE60026178T2 (de) | 2006-11-09 |
EP1259165B1 (de) | 2006-02-22 |
WO2001045565A2 (en) | 2001-06-28 |
US6546514B1 (en) | 2003-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FI20011417A (fi) | Menetelmä suojata elektroninen laite ja elektroninen laite | |
DE69904320D1 (de) | On-chip schaltung und verfahren zur speicherschaltungs-prüfung | |
DE60009646D1 (de) | Klebeverfahren und elektronisches Bauteil | |
DE60109238D1 (de) | Abgeschirmter Anschluss und Montageverfahren | |
DE10196149T1 (de) | DC/DC-Umformerverfahren und Schaltung | |
DE69924155D1 (de) | Fluoren-copolymere und daraus hergestellte vorrichtungen | |
FR2771843B1 (fr) | Transformateur en circuit integre | |
DE69921723D1 (de) | USB-Vorrichtung und USB- Knotenpunktvorrichtung | |
DE60026728D1 (de) | Bauteilbestückungseinrichtung und verfahren | |
DE60024375D1 (de) | Bauteilen-bestückungsverfahren und Einrichtung | |
DE60020737D1 (de) | Sic-einkristall und herstellungsverfahren dafür | |
DE60109997D1 (de) | Abgeschirmter Anschluss und Montageverfahren | |
DE69838362D1 (de) | Verbesserte integrierte Mehrschicht-Testflächen und Methode dafür | |
DE60134108D1 (de) | Eine elektronische Komponente und zugehöriges Herstellungsverfahren | |
FI20001797A (fi) | Monikerrospiirilevy ja sen valmistusmenetelmä | |
FI20000032A0 (fi) | Järjestely ja menetelmä pinnan tarkistamiseksi | |
DE60044969D1 (de) | Herstellungsverfahren einer integrierten schaltung | |
DE69819877D1 (de) | Elektronisches Mikrometer | |
DE60035917D1 (de) | Elektronisches Bauteil | |
DE69941874D1 (de) | Optielektronisches bauelement und herstellungsverfahren | |
DE69903961D1 (de) | Muscarinagonisten und antagonisten | |
DE69942053D1 (de) | Keramisches Elektronikbauteil | |
DE60035553D1 (de) | Hochfrequenzschaltungsplatte und seine Verbindungsstruktur | |
DE50013604D1 (de) | Schaltungsanordnung zur Kapazitätsmessung von Strukturen in einer integrierten Schaltung | |
IS6432A (is) | 4-Fenýl-1-píperazinýl, -píperidínýl og -tetrahýdrópýridýl afleiður |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: VOLMER, G., DIPL.-ING., PAT.-ANW., 52066 AACHEN |
|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |