DE60021819D1 - Datenschieberegister - Google Patents

Datenschieberegister

Info

Publication number
DE60021819D1
DE60021819D1 DE60021819T DE60021819T DE60021819D1 DE 60021819 D1 DE60021819 D1 DE 60021819D1 DE 60021819 T DE60021819 T DE 60021819T DE 60021819 T DE60021819 T DE 60021819T DE 60021819 D1 DE60021819 D1 DE 60021819D1
Authority
DE
Germany
Prior art keywords
shift register
data shift
data
register
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60021819T
Other languages
English (en)
Inventor
David Alan Edwards
Stephen James Wright
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE60021819D1 publication Critical patent/DE60021819D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
DE60021819T 1999-10-01 2000-09-25 Datenschieberegister Expired - Lifetime DE60021819D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/411,614 US6665816B1 (en) 1999-10-01 1999-10-01 Data shift register

Publications (1)

Publication Number Publication Date
DE60021819D1 true DE60021819D1 (de) 2005-09-15

Family

ID=23629638

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60021819T Expired - Lifetime DE60021819D1 (de) 1999-10-01 2000-09-25 Datenschieberegister

Country Status (3)

Country Link
US (1) US6665816B1 (de)
EP (1) EP1089085B1 (de)
DE (1) DE60021819D1 (de)

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US7519862B2 (en) * 2002-10-11 2009-04-14 Broadcom Corporation Software programmable verification tool having a single built-in self-test (BIST) module for testing and debugging multiple memory modules in a device under test (DUT)
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US7702964B2 (en) * 2004-05-11 2010-04-20 Qualcomm Incorporated Compression of data traces for an integrated circuit with multiple memories
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US7761762B2 (en) * 2004-12-02 2010-07-20 Texas Instruments Incorporated Adapter implemented background data transfers while tap in non-scan state
US7132823B2 (en) * 2005-01-21 2006-11-07 Microsoft Corporation Design for test for a high speed serial interface
KR101242602B1 (ko) * 2006-02-08 2013-03-19 삼성전자주식회사 테스트 회로를 내장한 시스템 온 칩
US7451367B2 (en) * 2006-02-14 2008-11-11 Atmel Corporation Accessing sequential data in microcontrollers
US20090323540A1 (en) * 2006-07-05 2009-12-31 Nxp B.V. Electronic device, system on chip and method for monitoring data traffic
DE102009012768B4 (de) * 2009-03-12 2021-12-30 Texas Instruments Deutschland Gmbh JTAG Nachrichtenbox
US8201025B2 (en) * 2009-04-29 2012-06-12 Freescale Semiconductor, Inc. Debug messaging with selective timestamp control
US8286032B2 (en) * 2009-04-29 2012-10-09 Freescale Semiconductor, Inc. Trace messaging device and methods thereof
US8589714B2 (en) 2009-12-18 2013-11-19 Texas Instruments Incorporated Falling clock edge JTAG bus routers
US8615610B2 (en) * 2011-09-29 2013-12-24 Freescale Semiconductor, Inc. Interface system and method with backward compatibility
US9330040B2 (en) * 2013-09-12 2016-05-03 Qualcomm Incorporated Serial configuration of a reconfigurable instruction cell array
WO2017072664A1 (en) * 2015-10-27 2017-05-04 Marvell World Trade Ltd. System and method for establishing a trusted diagnosis/debugging agent over a closed commodity device
US11258682B2 (en) * 2017-08-03 2022-02-22 Chicago Mercantile Exchange Inc. Compressed message tracing and parsing
US10386411B2 (en) 2017-08-23 2019-08-20 Stmicroelectronics International N.V. Sequential test access port selection in a JTAG interface
US10789153B2 (en) 2018-04-03 2020-09-29 Xilinx, Inc. Debug controller circuit
EP4279930A1 (de) * 2022-05-18 2023-11-22 B/E Aerospace, Inc. Boundary-scan-test für echtzeitstatusüberwachung

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Also Published As

Publication number Publication date
EP1089085A1 (de) 2001-04-04
EP1089085B1 (de) 2005-08-10
US6665816B1 (en) 2003-12-16

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Legal Events

Date Code Title Description
8332 No legal effect for de