DE60004399D1 - Verfahren und vorrichtung zur prüfung eines externen speichers mit einer eingebautem selbsttest - Google Patents
Verfahren und vorrichtung zur prüfung eines externen speichers mit einer eingebautem selbsttestInfo
- Publication number
- DE60004399D1 DE60004399D1 DE60004399T DE60004399T DE60004399D1 DE 60004399 D1 DE60004399 D1 DE 60004399D1 DE 60004399 T DE60004399 T DE 60004399T DE 60004399 T DE60004399 T DE 60004399T DE 60004399 D1 DE60004399 D1 DE 60004399D1
- Authority
- DE
- Germany
- Prior art keywords
- testing
- built
- self
- test
- external memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17348899P | 1999-12-29 | 1999-12-29 | |
| US173488P | 1999-12-29 | ||
| US09/517,517 US6675335B1 (en) | 1999-12-29 | 2000-03-02 | Method and apparatus for exercising external memory with a memory built-in self-test |
| US517517 | 2000-03-02 | ||
| PCT/US2000/015476 WO2001050474A1 (en) | 1999-12-29 | 2000-06-05 | Method and apparatus for exercising external memory with a memory built-in self-test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60004399D1 true DE60004399D1 (de) | 2003-09-11 |
| DE60004399T2 DE60004399T2 (de) | 2004-06-09 |
Family
ID=26869204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60004399T Expired - Lifetime DE60004399T2 (de) | 1999-12-29 | 2000-06-05 | Verfahren und vorrichtung zur prüfung eines externen speichers mit einer eingebautem selbsttest |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6675335B1 (de) |
| EP (1) | EP1242998B1 (de) |
| JP (1) | JP4630514B2 (de) |
| KR (1) | KR100776399B1 (de) |
| DE (1) | DE60004399T2 (de) |
| WO (1) | WO2001050474A1 (de) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6912202B1 (en) * | 2001-01-25 | 2005-06-28 | Advanced Micro Device, Inc. | Arrangement for testing network switch expansion port using external logic to emulate connected expansion port |
| US7096393B2 (en) * | 2002-12-20 | 2006-08-22 | Sun Microsystems, Inc. | Built-in self-test (BIST) of memory interconnect |
| US7526692B2 (en) * | 2004-09-30 | 2009-04-28 | International Business Machines Corporation | Diagnostic interface architecture for memory device |
| JP6503889B2 (ja) * | 2015-05-25 | 2019-04-24 | 富士通株式会社 | 演算処理装置、情報処理装置および演算処理装置の制御方法 |
| KR102649318B1 (ko) | 2016-12-29 | 2024-03-20 | 삼성전자주식회사 | 상태 회로를 포함하는 메모리 장치와 그것의 동작 방법 |
| US10663515B2 (en) | 2017-11-01 | 2020-05-26 | Nvidia Corp. | Method and apparatus to access high volume test data over high speed interfaces |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2745669B2 (ja) | 1989-04-27 | 1998-04-28 | ブラザー工業株式会社 | プリンタ |
| US5588115A (en) * | 1993-01-29 | 1996-12-24 | Teradyne, Inc. | Redundancy analyzer for automatic memory tester |
| US5423028A (en) | 1993-03-17 | 1995-06-06 | Dell Usa, L.P. | Diagnostic procedure for identifying presence of computer memory |
| US5410544A (en) * | 1993-06-30 | 1995-04-25 | Intel Corporation | External tester control for flash memory |
| JPH07160570A (ja) * | 1993-12-03 | 1995-06-23 | Canon Inc | 記憶制御装置 |
| US5675545A (en) * | 1995-09-08 | 1997-10-07 | Ambit Design Systems, Inc. | Method of forming a database that defines an integrated circuit memory with built in test circuitry |
| US5835502A (en) * | 1996-06-28 | 1998-11-10 | International Business Machines Corporation | Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme |
| US5958072A (en) * | 1997-01-13 | 1999-09-28 | Hewlett-Packard Company | Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware |
| US5812472A (en) | 1997-07-16 | 1998-09-22 | Tanisys Technology, Inc. | Nested loop method of identifying synchronous memories |
| US6080203A (en) * | 1997-12-18 | 2000-06-27 | Advanced Micro Devices, Inc. | Apparatus and method for designing a test and modeling system for a network switch device |
| US6345371B1 (en) * | 1999-05-05 | 2002-02-05 | Advanced Micro Devices Inc. | Method of performing diagnostic procedures on a queue structure |
-
2000
- 2000-03-02 US US09/517,517 patent/US6675335B1/en not_active Expired - Lifetime
- 2000-06-05 WO PCT/US2000/015476 patent/WO2001050474A1/en not_active Ceased
- 2000-06-05 DE DE60004399T patent/DE60004399T2/de not_active Expired - Lifetime
- 2000-06-05 KR KR1020027008590A patent/KR100776399B1/ko not_active Expired - Lifetime
- 2000-06-05 JP JP2001550759A patent/JP4630514B2/ja not_active Expired - Lifetime
- 2000-06-05 EP EP00941225A patent/EP1242998B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020065628A (ko) | 2002-08-13 |
| JP2003519851A (ja) | 2003-06-24 |
| KR100776399B1 (ko) | 2007-11-16 |
| DE60004399T2 (de) | 2004-06-09 |
| EP1242998B1 (de) | 2003-08-06 |
| WO2001050474A1 (en) | 2001-07-12 |
| JP4630514B2 (ja) | 2011-02-09 |
| US6675335B1 (en) | 2004-01-06 |
| EP1242998A1 (de) | 2002-09-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |