DE3940394A1 - Verfahren zum herstellen einer halbleitervorrichtung - Google Patents

Verfahren zum herstellen einer halbleitervorrichtung

Info

Publication number
DE3940394A1
DE3940394A1 DE19893940394 DE3940394A DE3940394A1 DE 3940394 A1 DE3940394 A1 DE 3940394A1 DE 19893940394 DE19893940394 DE 19893940394 DE 3940394 A DE3940394 A DE 3940394A DE 3940394 A1 DE3940394 A1 DE 3940394A1
Authority
DE
Germany
Prior art keywords
film
conductivity type
conductive film
dopant
oxidn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19893940394
Other languages
English (en)
Other versions
DE3940394C2 (de
Inventor
Hiromi Nakajima
Nobuyuki Itoh
Hiroyuki Nihira
Hiryo Tsukioka
Kenji Hirakawa
Shin-Ichi Taka
Hideki Takada
Yasuhiro Katsumata
Toshio Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3940394A1 publication Critical patent/DE3940394A1/de
Application granted granted Critical
Publication of DE3940394C2 publication Critical patent/DE3940394C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
DE19893940394 1988-12-06 1989-12-06 Verfahren zur Herstellung eines Bipolartransistors Expired - Fee Related DE3940394C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30690088A JPH02153534A (ja) 1988-12-06 1988-12-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3940394A1 true DE3940394A1 (de) 1990-06-07
DE3940394C2 DE3940394C2 (de) 1997-08-28

Family

ID=17962615

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19893940394 Expired - Fee Related DE3940394C2 (de) 1988-12-06 1989-12-06 Verfahren zur Herstellung eines Bipolartransistors

Country Status (2)

Country Link
JP (1) JPH02153534A (de)
DE (1) DE3940394C2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0527372A1 (de) * 1991-07-24 1993-02-17 Canon Kabushiki Kaisha Verfahren zur Herstellung eines Bipolar-Transistors
EP0650186A1 (de) * 1993-10-25 1995-04-26 Koninklijke Philips Electronics N.V. Herstellungsverfahren für eine Halbleitervorrichtung in welcher eine Halbleiterzone durch Diffusion aus einem polykristallinen Siliziumband geformd wird
EP0778615A1 (de) * 1995-12-06 1997-06-11 Nec Corporation Bipolar-Transistor und Verfahren zu seiner Herstellung
EP0942467A1 (de) * 1998-03-12 1999-09-15 Lucent Technologies Inc. Herstellungsverfahren für bipolare und BiCMOS Bauelemente

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54155778A (en) * 1978-05-30 1979-12-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture
JPS587862A (ja) * 1981-06-30 1983-01-17 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン バイポ−ラ型トランジスタ−構造体及びその製造方法
EP0042380B1 (de) * 1979-12-28 1986-03-19 International Business Machines Corporation Verfahren zum erreichen eines idealen fremdstoffkonzentrationsverlaufs für die basiszone eines transistors
US4581319A (en) * 1983-08-26 1986-04-08 Siemens Aktiengesellschaft Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits
JPH0681862A (ja) * 1992-09-07 1994-03-22 Nippondenso Co Ltd スタータクラッチ

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843539A (ja) * 1981-09-08 1983-03-14 Nec Corp 半導体装置
JPS5850755A (ja) * 1981-09-21 1983-03-25 Nippon Denso Co Ltd 半導体装置
JPS61283167A (ja) * 1985-06-07 1986-12-13 Nec Corp 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54155778A (en) * 1978-05-30 1979-12-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture
EP0042380B1 (de) * 1979-12-28 1986-03-19 International Business Machines Corporation Verfahren zum erreichen eines idealen fremdstoffkonzentrationsverlaufs für die basiszone eines transistors
JPS587862A (ja) * 1981-06-30 1983-01-17 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン バイポ−ラ型トランジスタ−構造体及びその製造方法
US4581319A (en) * 1983-08-26 1986-04-08 Siemens Aktiengesellschaft Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits
JPH0681862A (ja) * 1992-09-07 1994-03-22 Nippondenso Co Ltd スタータクラッチ

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JP 62-188370 A. In: Patents Abstracts of Japan, Sect. E, Vol. 12, 1988, No. 35 *
US-Buch: IEDM'86, 1986, S. 420 *
US-Z: IEEE Trans. on Electron. Devices, Bd. ED-53,April 1986, S. 526-531 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0527372A1 (de) * 1991-07-24 1993-02-17 Canon Kabushiki Kaisha Verfahren zur Herstellung eines Bipolar-Transistors
US5731240A (en) * 1991-07-24 1998-03-24 Canon Kabushiki Kaisha Manufacturing method for semiconductor depositing device
EP0650186A1 (de) * 1993-10-25 1995-04-26 Koninklijke Philips Electronics N.V. Herstellungsverfahren für eine Halbleitervorrichtung in welcher eine Halbleiterzone durch Diffusion aus einem polykristallinen Siliziumband geformd wird
BE1007670A3 (nl) * 1993-10-25 1995-09-12 Philips Electronics Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een halfgeleiderzone wordt gevormd door diffusie vanuit een strook polykristallijn silicium.
EP0778615A1 (de) * 1995-12-06 1997-06-11 Nec Corporation Bipolar-Transistor und Verfahren zu seiner Herstellung
US6034412A (en) * 1995-12-06 2000-03-07 Nec Corporation Semiconductor device and method of fabricating the same
US6165860A (en) * 1995-12-06 2000-12-26 Nec Corporation Semiconductor device with reduced photolithography steps
EP0942467A1 (de) * 1998-03-12 1999-09-15 Lucent Technologies Inc. Herstellungsverfahren für bipolare und BiCMOS Bauelemente

Also Published As

Publication number Publication date
JPH02153534A (ja) 1990-06-13
DE3940394C2 (de) 1997-08-28

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8381 Inventor (new situation)

Free format text: NAKAJIMA, HIROOMI, YOKOHAMA, JP ITOH, NOBUYUKI, TOKIO/TOKYO, JP NIHIRA, HIROYUKI, AYASE, KANAGAWA, JP TSUKIOKA, EIRYO, TOKOROZAWA, SAITAMA, JP HIRAKAWA, KENJI, YOKOHAMA, JP TAKA, SHIN-ICHI, YOKOSUKA, KANAGAWA, JP TAKADA, HIDEKI, YOKOHAMA, JP KATSUMATA, YASUHIRO, CHIGASAKI, KANAGAWA, JP YAMAGUCHI, TOSHIO, TOKIO/TOKYO, JP

8339 Ceased/non-payment of the annual fee