DE3853363D1 - Lastausgleichstechnik in einem gemeinsamen Speicher mit verteilter Struktur. - Google Patents

Lastausgleichstechnik in einem gemeinsamen Speicher mit verteilter Struktur.

Info

Publication number
DE3853363D1
DE3853363D1 DE3853363T DE3853363T DE3853363D1 DE 3853363 D1 DE3853363 D1 DE 3853363D1 DE 3853363 T DE3853363 T DE 3853363T DE 3853363 T DE3853363 T DE 3853363T DE 3853363 D1 DE3853363 D1 DE 3853363D1
Authority
DE
Germany
Prior art keywords
load balancing
shared memory
distributed structure
balancing technology
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853363T
Other languages
English (en)
Other versions
DE3853363T2 (de
Inventor
Phuoc Prof Dr Ing Tran-Gia
Andre Pauporte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3853363D1 publication Critical patent/DE3853363D1/de
Publication of DE3853363T2 publication Critical patent/DE3853363T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
DE19883853363 1988-12-23 1988-12-23 Lastausgleichstechnik in einem gemeinsamen Speicher mit verteilter Struktur. Expired - Fee Related DE3853363T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19880480101 EP0374337B1 (de) 1988-12-23 1988-12-23 Lastausgleichstechnik in einem gemeinsamen Speicher mit verteilter Struktur

Publications (2)

Publication Number Publication Date
DE3853363D1 true DE3853363D1 (de) 1995-04-20
DE3853363T2 DE3853363T2 (de) 1995-09-28

Family

ID=8200508

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883853363 Expired - Fee Related DE3853363T2 (de) 1988-12-23 1988-12-23 Lastausgleichstechnik in einem gemeinsamen Speicher mit verteilter Struktur.

Country Status (3)

Country Link
EP (1) EP0374337B1 (de)
JP (1) JPH02259944A (de)
DE (1) DE3853363T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems
US7006505B1 (en) 2000-10-23 2006-02-28 Bay Microsystems, Inc. Memory management system and algorithm for network processor architecture
US6532185B2 (en) * 2001-02-23 2003-03-11 International Business Machines Corporation Distribution of bank accesses in a multiple bank DRAM used as a data buffer
DE60238837D1 (de) 2001-05-17 2011-02-17 Alcatel Lucent Paketvermittlung mit verteiltem gemeinsam benutztem speicher
WO2003009543A2 (en) 2001-07-17 2003-01-30 Alcatel Internetworking, Inc. In-band message synchronization for distributed shared memory packet switch
WO2003088047A1 (en) * 2002-04-12 2003-10-23 Bay Microsystems, Inc. System and method for memory management within a network processor architecture
CA2382718C (en) 2002-04-12 2007-02-13 Ibm Canada Limited-Ibm Canada Limitee Memory balancing and optimization services
JPWO2012172683A1 (ja) * 2011-06-17 2015-02-23 富士通株式会社 演算処理装置、情報処理装置および演算処理装置の制御方法
US8627021B2 (en) 2011-08-31 2014-01-07 Qualcomm Incorporated Method and apparatus for load-based prefetch access
WO2013033882A1 (en) 2011-09-05 2013-03-14 Huawei Technologies Co., Ltd. A method and apparatus for storing data
US20160357456A1 (en) * 2015-06-03 2016-12-08 Kabushiki Kaisha Toshiba Memory device that divides write data into a plurality of data portions for data writing

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393459A (en) * 1980-07-17 1983-07-12 International Business Machines Corp. Status reporting with ancillary data
US4925311A (en) * 1986-02-10 1990-05-15 Teradata Corporation Dynamically partitionable parallel processors

Also Published As

Publication number Publication date
EP0374337A1 (de) 1990-06-27
JPH0581939B2 (de) 1993-11-16
EP0374337B1 (de) 1995-03-15
JPH02259944A (ja) 1990-10-22
DE3853363T2 (de) 1995-09-28

Similar Documents

Publication Publication Date Title
DE68917792D1 (de) Speicher.
DE68925631D1 (de) Speicheranordnung mit automatisch variabler Verschachtelung
DE3886114D1 (de) Halbleiterspeichergerät mit redundanter Speicherzellenmatrix.
DE68924306D1 (de) Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
DE3585517D1 (de) Mikroprozessor mit variabler speicherkapazitaet.
DE69002042D1 (de) Ausstellungsband versehen mit einem verstaerkten teil.
DE3771288D1 (de) Dynamischer speicher mit wahlfreiem zugriff.
DE68920247D1 (de) Kunststoffschaum mit Formgedächtnis.
DE68917388D1 (de) Rechneranlage mit einer zentralen Zwischenverbindung.
DE69018339D1 (de) Dynamische Speicheranordnung mit Rampenstruktur ausserhalb der Speicherzellenmatrix.
DE3773247D1 (de) Speicheranordnung mit reduziertem energieverbrauch.
DE3853363D1 (de) Lastausgleichstechnik in einem gemeinsamen Speicher mit verteilter Struktur.
DE68915395D1 (de) Dynamische Speicheranordnung mit verbessertem Leitungsnetz.
DE69414459D1 (de) Dynamischer Speicher mit Referenzzellen
DE3680543D1 (de) Lagersystem mit mehreren eingaengen.
DE69220465T2 (de) Halbleiteranordnung mit Speicherzelle
DE3850567D1 (de) DRAM-Zelle mit verstärkter Ladung.
DE3750175D1 (de) Mikroprozessor mit einem Cache-Speicher.
DE68918231D1 (de) Aufnahmegerät mit mehreren Entwicklungseinheiten.
DE68908170D1 (de) Anhaenger mit mehreren achsen.
NL193547B (nl) Halfgeleider-geheugenmatrix met reservegeheugenelementen.
DE68913316D1 (de) Rechnersystem mit einem hierarchisch organisierten Speicher.
DE68906171D1 (de) Speichersytem mit serienzugriff mit einer kaskaden-pufferschaltung.
DE58909149D1 (de) Addierzelle mit einem Summen- und einem Carryteil.
DE3855232D1 (de) Speichersteuersystem in einem Rechnersystem

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee