DE3780907D1 - Dotierter halbleiterdurchkontakt zum kontaktieren. - Google Patents

Dotierter halbleiterdurchkontakt zum kontaktieren.

Info

Publication number
DE3780907D1
DE3780907D1 DE8787402316T DE3780907T DE3780907D1 DE 3780907 D1 DE3780907 D1 DE 3780907D1 DE 8787402316 T DE8787402316 T DE 8787402316T DE 3780907 T DE3780907 T DE 3780907T DE 3780907 D1 DE3780907 D1 DE 3780907D1
Authority
DE
Germany
Prior art keywords
contact
doped semiconductor
semiconductor contact
doped
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787402316T
Other languages
English (en)
Other versions
DE3780907T2 (de
Inventor
Robert O Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE3780907D1 publication Critical patent/DE3780907D1/de
Publication of DE3780907T2 publication Critical patent/DE3780907T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3146—Carbon layers, e.g. diamond-like layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/934—Sheet resistance, i.e. dopant parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8787402316T 1986-10-17 1987-10-16 Dotierter halbleiterdurchkontakt zum kontaktieren. Expired - Fee Related DE3780907T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/920,251 US4722913A (en) 1986-10-17 1986-10-17 Doped semiconductor vias to contacts

Publications (2)

Publication Number Publication Date
DE3780907D1 true DE3780907D1 (de) 1992-09-10
DE3780907T2 DE3780907T2 (de) 1992-12-24

Family

ID=25443438

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787402316T Expired - Fee Related DE3780907T2 (de) 1986-10-17 1987-10-16 Dotierter halbleiterdurchkontakt zum kontaktieren.

Country Status (5)

Country Link
US (1) US4722913A (de)
EP (1) EP0265331B1 (de)
JP (1) JPS63120442A (de)
KR (1) KR960004589B1 (de)
DE (1) DE3780907T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972250A (en) * 1987-03-02 1990-11-20 Microwave Technology, Inc. Protective coating useful as passivation layer for semiconductor devices
US4843034A (en) * 1987-06-12 1989-06-27 Massachusetts Institute Of Technology Fabrication of interlayer conductive paths in integrated circuits
JPH07114237B2 (ja) * 1987-08-26 1995-12-06 株式会社東芝 半導体装置
JP2546696B2 (ja) * 1987-12-17 1996-10-23 富士通株式会社 シリコン炭化層構造
EP0327336B1 (de) * 1988-02-01 1997-12-10 Semiconductor Energy Laboratory Co., Ltd. Elektronische Anordnungen mit Kohlenstoffschichten
US5272361A (en) * 1989-06-30 1993-12-21 Semiconductor Energy Laboratory Co., Ltd. Field effect semiconductor device with immunity to hot carrier effects
JPH03192754A (ja) * 1989-12-22 1991-08-22 Omron Corp 半導体素子およびその製造方法
JPH05343350A (ja) * 1992-06-08 1993-12-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5514902A (en) 1993-09-16 1996-05-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having MOS transistor
US6927826B2 (en) * 1997-03-26 2005-08-09 Semiconductor Energy Labaratory Co., Ltd. Display device
JPH10268360A (ja) 1997-03-26 1998-10-09 Semiconductor Energy Lab Co Ltd 表示装置
US6350672B1 (en) * 1997-07-28 2002-02-26 United Microelectronics Corp. Interconnect structure with gas dielectric compatible with unlanded vias
JPH11307782A (ja) 1998-04-24 1999-11-05 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US6713234B2 (en) * 1999-02-18 2004-03-30 Micron Technology, Inc. Fabrication of semiconductor devices using anti-reflective coatings
US6475836B1 (en) * 1999-03-29 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3922708A (en) * 1974-03-04 1975-11-25 Ibm Method of producing high value ion implanted resistors
US4214918A (en) * 1978-10-12 1980-07-29 Stanford University Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam
US4392298A (en) * 1981-07-27 1983-07-12 Bell Telephone Laboratories, Incorporated Integrated circuit device connection process
US4511445A (en) * 1982-06-18 1985-04-16 At&T Bell Laboratories Process of enhancing conductivity of material
US4472210A (en) * 1983-01-07 1984-09-18 Rca Corporation Method of making a semiconductor device to improve conductivity of amorphous silicon films

Also Published As

Publication number Publication date
KR880005662A (ko) 1988-06-29
KR960004589B1 (ko) 1996-04-09
EP0265331A1 (de) 1988-04-27
JPS63120442A (ja) 1988-05-24
US4722913A (en) 1988-02-02
DE3780907T2 (de) 1992-12-24
EP0265331B1 (de) 1992-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SGS-THOMSON MICROELECTRONICS INC. (N.D.GES.DES STA

8339 Ceased/non-payment of the annual fee