DE3778783D1 - Matrix aus zusammengeschalteten duennschichttransistoren und ihre herstellung. - Google Patents

Matrix aus zusammengeschalteten duennschichttransistoren und ihre herstellung.

Info

Publication number
DE3778783D1
DE3778783D1 DE8787900833T DE3778783T DE3778783D1 DE 3778783 D1 DE3778783 D1 DE 3778783D1 DE 8787900833 T DE8787900833 T DE 8787900833T DE 3778783 T DE3778783 T DE 3778783T DE 3778783 D1 DE3778783 D1 DE 3778783D1
Authority
DE
Germany
Prior art keywords
matrix
production
thick film
film transistors
intermediate thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787900833T
Other languages
English (en)
Inventor
Bernard Diem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE3778783D1 publication Critical patent/DE3778783D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Landscapes

  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
DE8787900833T 1986-01-23 1987-01-22 Matrix aus zusammengeschalteten duennschichttransistoren und ihre herstellung. Expired - Lifetime DE3778783D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8600938A FR2593327B1 (fr) 1986-01-23 1986-01-23 Procede de fabrication d'un transistor en couches minces utilisant deux ou trois niveaux de masquage
PCT/FR1987/000023 WO1987004565A1 (fr) 1986-01-23 1987-01-22 Matrice de transistors en couches minces interconnectes et son procede de fabrication

Publications (1)

Publication Number Publication Date
DE3778783D1 true DE3778783D1 (de) 1992-06-11

Family

ID=9331416

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787900833T Expired - Lifetime DE3778783D1 (de) 1986-01-23 1987-01-22 Matrix aus zusammengeschalteten duennschichttransistoren und ihre herstellung.

Country Status (5)

Country Link
EP (1) EP0256053B1 (de)
JP (1) JPS63502220A (de)
DE (1) DE3778783D1 (de)
FR (1) FR2593327B1 (de)
WO (1) WO1987004565A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3752301T2 (de) * 1986-11-29 2000-03-23 Sharp K.K., Osaka Verfahren zur Herstellung eines Dünnschichttransistors
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
JP3172841B2 (ja) * 1992-02-19 2001-06-04 株式会社日立製作所 薄膜トランジスタとその製造方法及び液晶表示装置
US5545576A (en) * 1994-04-28 1996-08-13 Casio Computer Co., Ltd. Method for manufacturing a thin film transistor panel
US6882761B2 (en) * 2001-01-22 2005-04-19 The Furukawa Electric Co., Ltd. Silicon platform for optical modules

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024626A (en) * 1974-12-09 1977-05-24 Hughes Aircraft Company Method of making integrated transistor matrix for flat panel liquid crystal display
FR2533072B1 (fr) * 1982-09-14 1986-07-18 Coissard Pierre Procede de fabrication de circuits electroniques a base de transistors en couches minces et de condensateurs
JPS59119390A (ja) * 1982-12-25 1984-07-10 株式会社東芝 薄膜トランジスタ回路
JPS6066864A (ja) * 1983-09-22 1985-04-17 Seiko Instr & Electronics Ltd Ｍｉｓ型薄膜トランジスタ
FR2553579B1 (fr) * 1983-10-12 1985-12-27 Commissariat Energie Atomique Procede de fabrication d'un transistor en film mince a grille auto-alignee
JPS60105275A (ja) * 1983-11-11 1985-06-10 Seiko Instr & Electronics Ltd Ｍｉｓ型薄膜トランジスタ
JPH065681B2 (ja) * 1983-11-22 1994-01-19 松下電器産業株式会社 半導体装置の製造方法
JPS60160173A (ja) * 1984-01-30 1985-08-21 Sharp Corp 薄膜トランジスタ

Also Published As

Publication number Publication date
EP0256053B1 (de) 1992-05-06
WO1987004565A1 (fr) 1987-07-30
FR2593327A1 (fr) 1987-07-24
FR2593327B1 (fr) 1988-10-28
EP0256053A1 (de) 1988-02-24
JPS63502220A (ja) 1988-08-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee