DE3773558D1 - Verfahren und anordnung zur phaseneinstellung digitalsynchroner datenfluesse. - Google Patents

Verfahren und anordnung zur phaseneinstellung digitalsynchroner datenfluesse.

Info

Publication number
DE3773558D1
DE3773558D1 DE8787109798T DE3773558T DE3773558D1 DE 3773558 D1 DE3773558 D1 DE 3773558D1 DE 8787109798 T DE8787109798 T DE 8787109798T DE 3773558 T DE3773558 T DE 3773558T DE 3773558 D1 DE3773558 D1 DE 3773558D1
Authority
DE
Germany
Prior art keywords
arrangement
data flows
synchronous data
phase setting
digitally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787109798T
Other languages
English (en)
Inventor
Jean-Pierre Guerin
Meur Jean-Paul Le
Jean-Paul Morpain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of DE3773558D1 publication Critical patent/DE3773558D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE8787109798T 1986-07-10 1987-07-07 Verfahren und anordnung zur phaseneinstellung digitalsynchroner datenfluesse. Expired - Lifetime DE3773558D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8610093A FR2601534B1 (fr) 1986-07-10 1986-07-10 Procede et dispositif de calage en phase de trains numeriques synchrones

Publications (1)

Publication Number Publication Date
DE3773558D1 true DE3773558D1 (de) 1991-11-14

Family

ID=9337318

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787109798T Expired - Lifetime DE3773558D1 (de) 1986-07-10 1987-07-07 Verfahren und anordnung zur phaseneinstellung digitalsynchroner datenfluesse.

Country Status (6)

Country Link
US (1) US4780891A (de)
EP (1) EP0253281B1 (de)
JP (1) JPH07118704B2 (de)
CA (1) CA1269137A (de)
DE (1) DE3773558D1 (de)
FR (1) FR2601534B1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972444A (en) * 1988-07-14 1990-11-20 International Business Machines Corporation Digital phase-locked device and method
ATE101769T1 (de) * 1988-10-13 1994-03-15 Siemens Ag Verfahren und schaltungsanordnung zum empfang eines binaeren digitalsignals.
JPH02164153A (ja) * 1988-12-19 1990-06-25 Fujitsu Ltd ビット位相差吸収方式
JPH02192337A (ja) * 1989-01-20 1990-07-30 Fujitsu Ltd 位相調整回路
US5132554A (en) * 1989-03-29 1992-07-21 Sharp Kabushiki Kaisha Clock generating apparatus
AU642948B2 (en) * 1990-02-16 1993-11-04 Nokia Siemens Networks Gmbh & Co. Kg Process and device for beat recovery
US5333299A (en) * 1991-12-31 1994-07-26 International Business Machines Corporation Synchronization techniques for multimedia data streams
JP2871364B2 (ja) * 1992-12-16 1999-03-17 富士通株式会社 モデムの送信同期装置及び方法
US5737531A (en) * 1995-06-27 1998-04-07 International Business Machines Corporation System for synchronizing by transmitting control packet to omit blocks from transmission, and transmitting second control packet when the timing difference exceeds second predetermined threshold
DE19713660A1 (de) * 1997-04-02 1998-10-08 Siemens Nixdorf Inf Syst Phasenjustierung schneller paralleler Signale
WO1998049802A1 (de) * 1997-04-25 1998-11-05 Siemens Aktiengesellschaft Programmierbare phasenanpassung
US6621760B1 (en) * 2000-01-13 2003-09-16 Intel Corporation Method, apparatus, and system for high speed data transfer using source synchronous data strobe
US6973145B1 (en) * 2000-09-01 2005-12-06 Ut-Battelle, Llc Digital-data receiver synchronization method and apparatus
JP4118536B2 (ja) * 2001-07-03 2008-07-16 株式会社東芝 クロック遅延設定方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB968730A (de) * 1962-02-09
FR1422959A (fr) * 1964-11-13 1966-01-03 Thomson Houston Comp Francaise Perfectionnements aux dispositifs d'asservissement en phase
US3992580A (en) * 1975-04-24 1976-11-16 The United States Of America As Represented By The Secretary Of The Army Discrete control correction for synchronizing digital networks
US4229824A (en) * 1978-07-21 1980-10-21 Cubic Corporation Method and apparatus for synchronizing electrical signals
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
US4415984A (en) * 1980-06-25 1983-11-15 Burroughs Corporation Synchronous clock regenerator for binary serial data signals
US4451917A (en) * 1981-01-15 1984-05-29 Lynch Communication Systems, Inc. Method and apparatus for pulse train synchronization in PCM transceivers
IT8121477A0 (it) * 1981-04-30 1981-04-30 Italtel Spa Disposizione circuitale atta ad allineare tra loro una pluralita'di fasci pcm coerenti che pervengono ad un nodo di comunicazione.

Also Published As

Publication number Publication date
EP0253281B1 (de) 1991-10-09
FR2601534B1 (fr) 1993-07-30
FR2601534A1 (fr) 1988-01-15
EP0253281A1 (de) 1988-01-20
JPS6386935A (ja) 1988-04-18
US4780891A (en) 1988-10-25
JPH07118704B2 (ja) 1995-12-18
CA1269137A (fr) 1990-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition