DE3689276D1 - Verfahren zur Aktualisierung der Informationen in einem Adressenübersetzungspufferspeicher. - Google Patents

Verfahren zur Aktualisierung der Informationen in einem Adressenübersetzungspufferspeicher.

Info

Publication number
DE3689276D1
DE3689276D1 DE86108415T DE3689276T DE3689276D1 DE 3689276 D1 DE3689276 D1 DE 3689276D1 DE 86108415 T DE86108415 T DE 86108415T DE 3689276 T DE3689276 T DE 3689276T DE 3689276 D1 DE3689276 D1 DE 3689276D1
Authority
DE
Germany
Prior art keywords
updating
information
address translation
translation buffer
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE86108415T
Other languages
English (en)
Other versions
DE3689276T2 (de
Inventor
William R Bryg
Michael E Gardner
Steven C Boettner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE3689276D1 publication Critical patent/DE3689276D1/de
Application granted granted Critical
Publication of DE3689276T2 publication Critical patent/DE3689276T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE19863689276 1985-06-28 1986-06-20 Verfahren zur Aktualisierung der Informationen in einem Adressenübersetzungspufferspeicher. Expired - Lifetime DE3689276T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US75039085A 1985-06-28 1985-06-28

Publications (2)

Publication Number Publication Date
DE3689276D1 true DE3689276D1 (de) 1993-12-16
DE3689276T2 DE3689276T2 (de) 1994-02-24

Family

ID=25017671

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863689276 Expired - Lifetime DE3689276T2 (de) 1985-06-28 1986-06-20 Verfahren zur Aktualisierung der Informationen in einem Adressenübersetzungspufferspeicher.

Country Status (4)

Country Link
EP (1) EP0212129B1 (de)
JP (1) JPH083805B2 (de)
CA (1) CA1262287A (de)
DE (1) DE3689276T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503702B2 (ja) * 1989-12-19 1996-06-05 日本電気株式会社 アドレス変換装置
DE69130757T2 (de) * 1990-11-30 1999-07-29 Toshiba Kawasaki Kk Ausführungsvorrichtung für bedingte Verzweigungsbefehle
DE4410060B4 (de) * 1993-04-08 2006-02-09 Hewlett-Packard Development Co., L.P., Houston Übersetzungsvorrichtung zum Umsetzen einer virtuellen Speicheradresse in eine physikalische Speicheradresse
US5515522A (en) * 1994-02-24 1996-05-07 Hewlett-Packard Company Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache
US7765366B2 (en) 2005-06-23 2010-07-27 Intel Corporation Memory micro-tiling
US8332598B2 (en) 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering
US7558941B2 (en) 2005-06-30 2009-07-07 Intel Corporation Automatic detection of micro-tile enabled memory
US8253751B2 (en) 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US8878860B2 (en) 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
GB2499168B (en) 2010-11-26 2014-04-16 Ibm Cache coherency control method, system, and program

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5734586B2 (de) * 1975-02-03 1982-07-23
JPS6047622B2 (ja) * 1981-09-30 1985-10-22 富士通株式会社 動的アドレス変換制御方式
JPH0658646B2 (ja) * 1982-12-30 1994-08-03 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション デ−タ持続性が制御される仮想記憶アドレス変換機構
JPS6095658A (ja) * 1983-10-28 1985-05-29 Toshiba Corp 仮想記憶制御方法

Also Published As

Publication number Publication date
EP0212129A3 (en) 1990-05-30
JPS623357A (ja) 1987-01-09
EP0212129B1 (de) 1993-11-10
EP0212129A2 (de) 1987-03-04
JPH083805B2 (ja) 1996-01-17
DE3689276T2 (de) 1994-02-24
CA1262287A (en) 1989-10-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE