DE3689112D1 - Zugriffssteuerungssystem fuer den befehlskode. - Google Patents

Zugriffssteuerungssystem fuer den befehlskode.

Info

Publication number
DE3689112D1
DE3689112D1 DE86118090T DE3689112T DE3689112D1 DE 3689112 D1 DE3689112 D1 DE 3689112D1 DE 86118090 T DE86118090 T DE 86118090T DE 3689112 T DE3689112 T DE 3689112T DE 3689112 D1 DE3689112 D1 DE 3689112D1
Authority
DE
Germany
Prior art keywords
control system
access control
command code
command
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE86118090T
Other languages
English (en)
Other versions
DE3689112T2 (de
Inventor
Yasushi C O Nec Corporatio Ooi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3689112D1 publication Critical patent/DE3689112D1/de
Application granted granted Critical
Publication of DE3689112T2 publication Critical patent/DE3689112T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE86118090T 1985-12-26 1986-12-29 Zugriffssteuerungssystem für den Befehlskode. Expired - Fee Related DE3689112T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60294162A JPS62152043A (ja) 1985-12-26 1985-12-26 命令コ−ドアクセス制御方式

Publications (2)

Publication Number Publication Date
DE3689112D1 true DE3689112D1 (de) 1993-11-04
DE3689112T2 DE3689112T2 (de) 1994-04-21

Family

ID=17804115

Family Applications (1)

Application Number Title Priority Date Filing Date
DE86118090T Expired - Fee Related DE3689112T2 (de) 1985-12-26 1986-12-29 Zugriffssteuerungssystem für den Befehlskode.

Country Status (4)

Country Link
US (1) US4924376A (de)
EP (1) EP0227118B1 (de)
JP (1) JPS62152043A (de)
DE (1) DE3689112T2 (de)

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EP0284100A3 (de) * 1987-03-27 1991-10-09 Nec Corporation Informationsprozessor mit einer Befehlsvorabruffunktion
US5222223A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Method and apparatus for ordering and queueing multiple memory requests
US5179673A (en) * 1989-12-18 1993-01-12 Digital Equipment Corporation Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
US5257360A (en) * 1990-03-23 1993-10-26 Advanced Micro Devices,Inc. Re-configurable block length cache
US5784711A (en) * 1990-05-18 1998-07-21 Philips Electronics North America Corporation Data cache prefetching under control of instruction cache
JP2532300B2 (ja) * 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
US5226138A (en) * 1990-11-27 1993-07-06 Sun Microsystems, Inc. Method for selectively transferring data instructions to a cache memory
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
JP2779557B2 (ja) * 1991-07-09 1998-07-23 三菱電機株式会社 並列演算処理装置
JPH05100848A (ja) * 1991-10-11 1993-04-23 Matsushita Electric Ind Co Ltd 命令プリフエツチ装置
US5285527A (en) * 1991-12-11 1994-02-08 Northern Telecom Limited Predictive historical cache memory
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
US5363490A (en) * 1992-02-03 1994-11-08 Unisys Corporation Apparatus for and method of conditionally aborting an instruction within a pipelined architecture
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
DE69311330T2 (de) 1992-03-31 1997-09-25 Seiko Epson Corp., Tokio/Tokyo Befehlsablauffolgeplanung von einem risc-superskalarprozessor
EP0638183B1 (de) 1992-05-01 1997-03-05 Seiko Epson Corporation Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
WO1994016384A1 (en) 1992-12-31 1994-07-21 Seiko Epson Corporation System and method for register renaming
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5724533A (en) * 1995-11-17 1998-03-03 Unisys Corporation High performance instruction data path
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5761452A (en) * 1996-03-18 1998-06-02 Advanced Micro Devices, Inc. Bus arbiter method and system
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
US5796972A (en) * 1997-01-14 1998-08-18 Unisys Corporation Method and apparatus for performing microcode paging during instruction execution in an instruction processor
US6275924B1 (en) * 1998-09-15 2001-08-14 Texas Instruments Incorporated System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time
US6580431B1 (en) 1999-03-04 2003-06-17 Nexmem System, method, and computer program product for intelligent memory to accelerate processes
US20020135611A1 (en) * 1999-03-04 2002-09-26 Trevor Deosaran Remote performance management to accelerate distributed processes
JP3838405B2 (ja) * 2000-02-01 2006-10-25 富士通株式会社 中央処理装置および中央処理システム
US7139898B1 (en) * 2000-11-03 2006-11-21 Mips Technologies, Inc. Fetch and dispatch disassociation apparatus for multistreaming processors
US7114063B1 (en) 2000-12-01 2006-09-26 Unisys Corporation Condition indicator for use by a conditional branch instruction
WO2006026123A2 (en) * 2004-08-31 2006-03-09 Silicon Optix Method and apparatus for executing instructions from an auxiliary data stream
US8516466B2 (en) * 2010-06-30 2013-08-20 International Business Machines Corporation Optimization of automated system-managed storage operations
JP5793061B2 (ja) * 2011-11-02 2015-10-14 ルネサスエレクトロニクス株式会社 キャッシュメモリ装置、キャッシュ制御方法、およびマイクロプロセッサシステム

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3348209A (en) * 1964-11-27 1967-10-17 Rca Corp Buffer
US3898624A (en) * 1973-06-14 1975-08-05 Amdahl Corp Data processing system with variable prefetch and replacement algorithms
JPS5837585B2 (ja) * 1975-09-30 1983-08-17 株式会社東芝 ケイサンキソウチ
JPS5247638A (en) * 1975-10-15 1977-04-15 Toshiba Corp Information processing device
JPS5248440A (en) * 1975-10-15 1977-04-18 Toshiba Corp Memory access control system
US4057846A (en) * 1976-06-07 1977-11-08 International Business Machines Corporation Bus steering structure for low cost pipelined processor system
US4442484A (en) * 1980-10-14 1984-04-10 Intel Corporation Microprocessor memory management and protection mechanism
US4453214A (en) * 1981-09-08 1984-06-05 Sperry Corporation Bus arbitrating circuit
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
US4648034A (en) * 1984-08-27 1987-03-03 Zilog, Inc. Busy signal interface between master and slave processors in a computer system

Also Published As

Publication number Publication date
US4924376A (en) 1990-05-08
JPS62152043A (ja) 1987-07-07
EP0227118B1 (de) 1993-09-29
EP0227118A3 (en) 1989-11-08
DE3689112T2 (de) 1994-04-21
EP0227118A2 (de) 1987-07-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee