DE3688269D1 - Taktsynchronisierer fuer zugriffsschnittstelle. - Google Patents

Taktsynchronisierer fuer zugriffsschnittstelle.

Info

Publication number
DE3688269D1
DE3688269D1 DE8686305539T DE3688269T DE3688269D1 DE 3688269 D1 DE3688269 D1 DE 3688269D1 DE 8686305539 T DE8686305539 T DE 8686305539T DE 3688269 T DE3688269 T DE 3688269T DE 3688269 D1 DE3688269 D1 DE 3688269D1
Authority
DE
Germany
Prior art keywords
clock
acquisition
port
generated
jitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686305539T
Other languages
English (en)
Other versions
DE3688269T2 (de
Inventor
Nallepilli S Ramesh
Subramanian Narashimhan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE3688269D1 publication Critical patent/DE3688269D1/de
Application granted granted Critical
Publication of DE3688269T2 publication Critical patent/DE3688269T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Communication Control (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Separation Of Suspended Particles By Flocculating Agents (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
DE8686305539T 1985-07-26 1986-07-18 Taktsynchronisierer fuer zugriffsschnittstelle. Expired - Fee Related DE3688269T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/759,623 US4737722A (en) 1985-07-26 1985-07-26 Serial port synchronizer

Publications (2)

Publication Number Publication Date
DE3688269D1 true DE3688269D1 (de) 1993-05-19
DE3688269T2 DE3688269T2 (de) 1993-07-29

Family

ID=25056360

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686305539T Expired - Fee Related DE3688269T2 (de) 1985-07-26 1986-07-18 Taktsynchronisierer fuer zugriffsschnittstelle.

Country Status (5)

Country Link
US (1) US4737722A (de)
EP (1) EP0210799B1 (de)
JP (1) JP2578590B2 (de)
AT (1) ATE88307T1 (de)
DE (1) DE3688269T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808937A (en) * 1986-07-15 1989-02-28 Hayes Microcomputer Products, Inc. Phase-locked loop for a modem
US4818950A (en) * 1987-04-24 1989-04-04 Ncr Corporation Low jitter phase-locked loop
JP2787725B2 (ja) * 1990-02-14 1998-08-20 第一電子工業株式会社 データ・クロックのタイミング合わせ回路
DE69224322D1 (de) * 1991-05-31 1998-03-12 Koninkl Philips Electronics Nv Einrichtung zur Übertragung von Daten mit variabler Bitrate zwischen einem Modem und einer synchronen Endeinrichtung
GB2390000A (en) * 2002-06-18 2003-12-24 Zarlink Semiconductor Inc Frame Boundary Discriminator to Remove Jitter
US10525234B2 (en) 2010-09-10 2020-01-07 C. R. Bard, Inc. Antimicrobial/haemostatic interface pad for placement between percutaneously placed medical device and patient skin
JP2016092445A (ja) * 2014-10-29 2016-05-23 株式会社リコー シリアル通信システム
CN108604979B (zh) * 2016-02-02 2021-05-18 马维尔亚洲私人有限公司 用于网络同步的方法和装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3363183A (en) * 1965-07-13 1968-01-09 Ibm Self-correcting clock for a data transmission system
US4014025A (en) * 1975-03-24 1977-03-22 The Cessna Aircraft Company Scalloping suppression system and method
US3983498A (en) * 1975-11-13 1976-09-28 Motorola, Inc. Digital phase lock loop
US4216544A (en) * 1978-09-19 1980-08-05 Northern Telecom Limited Digital clock recovery circuit
JPS561824A (en) * 1979-07-12 1981-01-10 Toshio Takayama Seedling growing box
JPS58205336A (ja) * 1982-05-26 1983-11-30 Hitachi Ltd デイジタル位相同期回路
US4600845A (en) * 1983-12-30 1986-07-15 The Charles Stark Draper Laboratory, Inc. Fault-tolerant clock system
SE8403225D0 (sv) * 1984-06-15 1984-06-15 Asea Ab Metod for fastlast sampling av en periodisk signal

Also Published As

Publication number Publication date
ATE88307T1 (de) 1993-04-15
JPS6226919A (ja) 1987-02-04
EP0210799B1 (de) 1993-04-14
EP0210799A2 (de) 1987-02-04
EP0210799A3 (en) 1987-07-29
JP2578590B2 (ja) 1997-02-05
US4737722A (en) 1988-04-12
DE3688269T2 (de) 1993-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee