DE3672559D1 - Verfahren zum herstellen einer ladungstransportanordnung und danach hergestellte ladungstransportanordnung. - Google Patents

Verfahren zum herstellen einer ladungstransportanordnung und danach hergestellte ladungstransportanordnung.

Info

Publication number
DE3672559D1
DE3672559D1 DE8686402263T DE3672559T DE3672559D1 DE 3672559 D1 DE3672559 D1 DE 3672559D1 DE 8686402263 T DE8686402263 T DE 8686402263T DE 3672559 T DE3672559 T DE 3672559T DE 3672559 D1 DE3672559 D1 DE 3672559D1
Authority
DE
Germany
Prior art keywords
cargo transport
transport arrangement
producing
produced
cargo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686402263T
Other languages
English (en)
Inventor
Pierre Blanchard
Michel Carquet
Philippe Warenbourg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE3672559D1 publication Critical patent/DE3672559D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
    • H01L29/66954—Charge transfer devices with an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42396—Gate electrodes for field effect devices for charge coupled devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
DE8686402263T 1985-10-18 1986-10-10 Verfahren zum herstellen einer ladungstransportanordnung und danach hergestellte ladungstransportanordnung. Expired - Fee Related DE3672559D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8515503A FR2589003B1 (fr) 1985-10-18 1985-10-18 Procede de realisation d'un dispositif a transfert de charge et dispositif a transfert de charge mettant en oeuvre ce procede

Publications (1)

Publication Number Publication Date
DE3672559D1 true DE3672559D1 (de) 1990-08-16

Family

ID=9323974

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686402263T Expired - Fee Related DE3672559D1 (de) 1985-10-18 1986-10-10 Verfahren zum herstellen einer ladungstransportanordnung und danach hergestellte ladungstransportanordnung.

Country Status (5)

Country Link
US (1) US4774199A (de)
EP (1) EP0220120B1 (de)
JP (1) JPS6298773A (de)
DE (1) DE3672559D1 (de)
FR (1) FR2589003B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4900688A (en) * 1987-06-25 1990-02-13 The United States Of America As Represented By The Secretary Of The Air Force Pseudo uniphase charge coupled device fabrication by self-aligned virtual barrier and virtual gate formation
DE3817153A1 (de) * 1988-05-19 1989-11-30 Messerschmitt Boelkow Blohm Halbleiter-bauelement
FR2679379B1 (fr) * 1991-07-16 1997-04-25 Thomson Composants Militaires Procede de fabrication de circuits integres avec electrodes tres etroites.
US5369040A (en) * 1992-05-18 1994-11-29 Westinghouse Electric Corporation Method of making transparent polysilicon gate for imaging arrays

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4347656A (en) * 1970-10-29 1982-09-07 Bell Telephone Laboratories, Incorporated Method of fabricating polysilicon electrodes
US3795847A (en) * 1973-03-26 1974-03-05 Gen Electric Method and apparatus for storing and transferring information
US4001861A (en) * 1973-10-12 1977-01-04 The United States Of America As Represented By The Secretary Of The Navy Double-layer, polysilicon, two-phase, charge coupled device
US4290187A (en) * 1973-10-12 1981-09-22 Siemens Aktiengesellschaft Method of making charge-coupled arrangement in the two-phase technique
US3943543A (en) * 1974-07-26 1976-03-09 Texas Instruments Incorporated Three level electrode configuration for three phase charge coupled device
JPS5849035B2 (ja) * 1976-08-16 1983-11-01 株式会社東芝 電荷転送素子
US4365261A (en) * 1977-08-26 1982-12-21 Texas Instruments Incorporated Co-planar barrier-type charge coupled device with enhanced storage capacity and decreased leakage current
NL8004328A (nl) * 1980-07-29 1982-03-01 Philips Nv Schakelinrichting voor het ontladen van een capaciteit.
US4613402A (en) * 1985-07-01 1986-09-23 Eastman Kodak Company Method of making edge-aligned implants and electrodes therefor

Also Published As

Publication number Publication date
US4774199A (en) 1988-09-27
FR2589003A1 (fr) 1987-04-24
EP0220120B1 (de) 1990-07-11
FR2589003B1 (fr) 1987-11-20
EP0220120A1 (de) 1987-04-29
JPS6298773A (ja) 1987-05-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee