DE3587480T2 - Arithmetische operationseinheit und arithmetische operationsschaltung. - Google Patents

Arithmetische operationseinheit und arithmetische operationsschaltung.

Info

Publication number
DE3587480T2
DE3587480T2 DE85101766T DE3587480T DE3587480T2 DE 3587480 T2 DE3587480 T2 DE 3587480T2 DE 85101766 T DE85101766 T DE 85101766T DE 3587480 T DE3587480 T DE 3587480T DE 3587480 T2 DE3587480 T2 DE 3587480T2
Authority
DE
Germany
Prior art keywords
arithmetic operating
circuit
operating unit
unit
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE85101766T
Other languages
English (en)
Other versions
DE3587480D1 (de
Inventor
Hideo Maejima
Takashi Hotta
Ikuro Masuda
Masahiro Iwamura
Kouzaburou Kurita
Masahiro Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59031257A external-priority patent/JP2609581B2/ja
Priority claimed from JP60002020A external-priority patent/JPH0721744B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3587480D1 publication Critical patent/DE3587480D1/de
Application granted granted Critical
Publication of DE3587480T2 publication Critical patent/DE3587480T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
DE85101766T 1984-02-20 1985-02-18 Arithmetische operationseinheit und arithmetische operationsschaltung. Expired - Fee Related DE3587480T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59031257A JP2609581B2 (ja) 1984-02-20 1984-02-20 プロセッサ
JP60002020A JPH0721744B2 (ja) 1985-01-11 1985-01-11 バスラインのプリチャージ回路

Publications (2)

Publication Number Publication Date
DE3587480D1 DE3587480D1 (de) 1993-09-02
DE3587480T2 true DE3587480T2 (de) 1993-11-04

Family

ID=26335332

Family Applications (1)

Application Number Title Priority Date Filing Date
DE85101766T Expired - Fee Related DE3587480T2 (de) 1984-02-20 1985-02-18 Arithmetische operationseinheit und arithmetische operationsschaltung.

Country Status (3)

Country Link
US (2) US4789958A (de)
EP (1) EP0152939B1 (de)
DE (1) DE3587480T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6398729A (ja) * 1986-10-15 1988-04-30 Fujitsu Ltd バレルシフタ
US4918642A (en) * 1988-03-29 1990-04-17 Chang Chih C Isolated carry propagation fast adder
US5398206A (en) * 1990-03-02 1995-03-14 Hitachi, Ltd. Semiconductor memory device with data error compensation
US5367691A (en) * 1991-04-15 1994-11-22 Motorola, Inc. Pipe-staggered apparatus and method utilizing carry look-ahead signal processing
DE10050589B4 (de) 2000-02-18 2006-04-06 Hewlett-Packard Development Co., L.P., Houston Vorrichtung und Verfahren zur Verwendung beim Durchführen einer Gleitkomma-Multiplizier-Akkumulier-Operation
US8135768B2 (en) * 2005-03-02 2012-03-13 Mtekvision Co., Ltd. Adder with reduced capacitance
CN101692200B (zh) * 2008-03-11 2018-02-02 魏营隆 数字绳码编码解码及加减乘除倒数算术电路设计的方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3601628A (en) * 1969-06-25 1971-08-24 Texas Instruments Inc Precharge mos-bipolar output buffer
US4037094A (en) * 1971-08-31 1977-07-19 Texas Instruments Incorporated Multi-functional arithmetic and logical unit
US3757308A (en) * 1971-09-03 1973-09-04 Texas Instruments Inc Data processor
US3728532A (en) * 1972-01-21 1973-04-17 Rca Corp Carry skip-ahead network
US3919536A (en) * 1973-09-13 1975-11-11 Texas Instruments Inc Precharged digital adder and carry circuit
JPS5325375A (en) * 1976-07-31 1978-03-09 Nippon Gakki Seizo Kk Semiconductor integrated circuit devi ce
JPS53135249A (en) * 1977-04-30 1978-11-25 Nippon Gakki Seizo Kk Logic circuit system for integration
JPS5490941A (en) * 1977-12-26 1979-07-19 Hitachi Ltd Driving circuit of tristate type
US4229803A (en) * 1978-06-02 1980-10-21 Texas Instruments Incorporated I2 L Full adder and ALU
JPS5525858A (en) * 1978-08-11 1980-02-23 Nec Corp Memory unit
US4276616A (en) * 1979-04-23 1981-06-30 Fairchild Camera & Instrument Corp. Merged bipolar/field-effect bistable memory cell
JPS5625290A (en) * 1979-08-07 1981-03-11 Nec Corp Semiconductor circuit
US4425623A (en) * 1981-07-14 1984-01-10 Rockwell International Corporation Lookahead carry circuit apparatus
JPS5833739A (ja) * 1981-08-21 1983-02-28 Toshiba Corp バスライン駆動回路
US4567561A (en) * 1981-12-24 1986-01-28 International Business Machines Corp. Large scale integration data processor signal transfer mechanism
US4437171A (en) * 1982-01-07 1984-03-13 Intel Corporation ECL Compatible CMOS memory
US4504924A (en) * 1982-06-28 1985-03-12 International Business Machines Corporation Carry lookahead logical mechanism using affirmatively referenced transfer gates
JPH0783252B2 (ja) * 1982-07-12 1995-09-06 株式会社日立製作所 半導体集積回路装置
DE3380105D1 (en) * 1982-09-29 1989-07-27 Hitachi Ltd Semiconductor integrated circuit device
JPS60125015A (ja) * 1983-12-12 1985-07-04 Hitachi Ltd インバ−タ回路
JPH0616585B2 (ja) * 1983-12-16 1994-03-02 株式会社日立製作所 バツフア回路
JPS60136989A (ja) * 1983-12-26 1985-07-20 Hitachi Ltd 半導体記憶装置の書き込み回路
JPH0795395B2 (ja) * 1984-02-13 1995-10-11 株式会社日立製作所 半導体集積回路
US4563751A (en) * 1984-04-26 1986-01-07 Motorola, Inc. Carry propagate adder circuit which differentially senses a carry input

Also Published As

Publication number Publication date
EP0152939A3 (en) 1989-07-19
US4789958A (en) 1988-12-06
DE3587480D1 (de) 1993-09-02
US5117382A (en) 1992-05-26
EP0152939A2 (de) 1985-08-28
EP0152939B1 (de) 1993-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee