DE3586954D1 - Anzeigesteuereinrichtung. - Google Patents

Anzeigesteuereinrichtung.

Info

Publication number
DE3586954D1
DE3586954D1 DE8585101561T DE3586954T DE3586954D1 DE 3586954 D1 DE3586954 D1 DE 3586954D1 DE 8585101561 T DE8585101561 T DE 8585101561T DE 3586954 T DE3586954 T DE 3586954T DE 3586954 D1 DE3586954 D1 DE 3586954D1
Authority
DE
Germany
Prior art keywords
control device
display control
display
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585101561T
Other languages
English (en)
Other versions
DE3586954T2 (de
Inventor
Takatoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASCII Corp
Original Assignee
ASCII Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASCII Corp filed Critical ASCII Corp
Publication of DE3586954D1 publication Critical patent/DE3586954D1/de
Application granted granted Critical
Publication of DE3586954T2 publication Critical patent/DE3586954T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G09G5/246—Generation of individual character patterns of ideographic or arabic-like characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
DE19853586954 1984-02-20 1985-02-13 Anzeigesteuereinrichtung. Expired - Fee Related DE3586954T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59028784A JPS60173580A (ja) 1984-02-20 1984-02-20 表示制御装置

Publications (2)

Publication Number Publication Date
DE3586954D1 true DE3586954D1 (de) 1993-02-18
DE3586954T2 DE3586954T2 (de) 1993-06-03

Family

ID=12258041

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853586954 Expired - Fee Related DE3586954T2 (de) 1984-02-20 1985-02-13 Anzeigesteuereinrichtung.

Country Status (4)

Country Link
EP (1) EP0155499B1 (de)
JP (1) JPS60173580A (de)
CA (1) CA1228931A (de)
DE (1) DE3586954T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2210239B (en) * 1987-09-19 1992-06-17 Hudson Soft Co Ltd An apparatus for controlling the access of a video memory
GB2246935B (en) * 1987-09-19 1992-05-20 Hudson Soft Co Ltd An apparatus for the control of an access to a video memory
US7827424B2 (en) * 2004-07-29 2010-11-02 Ati Technologies Ulc Dynamic clock control circuit and method
US7800621B2 (en) 2005-05-16 2010-09-21 Ati Technologies Inc. Apparatus and methods for control of a memory controller
US8799685B2 (en) 2010-08-25 2014-08-05 Advanced Micro Devices, Inc. Circuits and methods for providing adjustable power consumption

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197590A (en) * 1976-01-19 1980-04-08 Nugraphics, Inc. Method for dynamically viewing image elements stored in a random access memory array
JPS5326539A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Data exchenge system
GB2016757A (en) * 1978-02-21 1979-09-26 Data General Corp Display Terminal
JPS54139433A (en) * 1978-04-21 1979-10-29 Hitachi Ltd Decision system for end of writing
JPS54139431A (en) * 1978-04-21 1979-10-29 Hitachi Ltd Crt display unit
US4240140A (en) * 1978-12-26 1980-12-16 Honeywell Information Systems Inc. CRT display terminal priority interrupt apparatus for generating vectored addresses
JPS5674738A (en) * 1979-11-21 1981-06-20 Toshiba Corp Transfer system of display data
US4394645A (en) * 1981-09-10 1983-07-19 Sensormatic Electronics Corporation Electrical surveillance apparatus with moveable antenna elements
JPS5960480A (ja) * 1982-09-29 1984-04-06 フアナツク株式会社 デイスプレイ装置

Also Published As

Publication number Publication date
EP0155499A2 (de) 1985-09-25
EP0155499A3 (en) 1990-09-12
JPS60173580A (ja) 1985-09-06
DE3586954T2 (de) 1993-06-03
EP0155499B1 (de) 1993-01-07
CA1228931A (en) 1987-11-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee