DE3586233D1 - Arithmetischer prozessor mit paralleler akkumulierfunktion. - Google Patents

Arithmetischer prozessor mit paralleler akkumulierfunktion.

Info

Publication number
DE3586233D1
DE3586233D1 DE8585112408T DE3586233T DE3586233D1 DE 3586233 D1 DE3586233 D1 DE 3586233D1 DE 8585112408 T DE8585112408 T DE 8585112408T DE 3586233 T DE3586233 T DE 3586233T DE 3586233 D1 DE3586233 D1 DE 3586233D1
Authority
DE
Germany
Prior art keywords
arithmetic processor
accumulation function
parallel accumulation
parallel
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585112408T
Other languages
English (en)
Inventor
Richard Douglas Degroot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3586233D1 publication Critical patent/DE3586233D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
DE8585112408T 1984-10-25 1985-10-01 Arithmetischer prozessor mit paralleler akkumulierfunktion. Expired - Lifetime DE3586233D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/664,739 US4683547A (en) 1984-10-25 1984-10-25 Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance

Publications (1)

Publication Number Publication Date
DE3586233D1 true DE3586233D1 (de) 1992-07-23

Family

ID=24667259

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585112408T Expired - Lifetime DE3586233D1 (de) 1984-10-25 1985-10-01 Arithmetischer prozessor mit paralleler akkumulierfunktion.

Country Status (4)

Country Link
US (1) US4683547A (de)
EP (1) EP0180048B1 (de)
JP (1) JPS61107431A (de)
DE (1) DE3586233D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0205193B1 (de) * 1985-06-17 1996-10-23 Nec Corporation Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers
US4841467A (en) * 1987-10-05 1989-06-20 General Electric Company Architecture to implement floating point multiply/accumulate operations
US4916651A (en) * 1988-01-29 1990-04-10 Texas Instruments Incorporated Floating point processor architecture
JPH0769821B2 (ja) * 1988-03-04 1995-07-31 日本電気株式会社 情報処理装置におけるバイパスライン制御方式
US5212662A (en) * 1989-01-13 1993-05-18 International Business Machines Corporation Floating point arithmetic two cycle data flow
US4999802A (en) * 1989-01-13 1991-03-12 International Business Machines Corporation Floating point arithmetic two cycle data flow
US5128891A (en) * 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. High speed divider with square root capability
US5058048A (en) * 1990-04-02 1991-10-15 Advanced Micro Devices, Inc. Normalizing pipelined floating point processing unit
US5128888A (en) * 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. Arithmetic unit having multiple accumulators
US5053631A (en) * 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit
JPH04127364A (ja) * 1990-09-19 1992-04-28 Nec Corp 積和算器
US5128890A (en) * 1991-05-06 1992-07-07 Motorola, Inc. Apparatus for performing multiplications with reduced power and a method therefor
EP0623874A1 (de) * 1993-05-03 1994-11-09 International Business Machines Corporation Verfahren zur Ausführung von Befehlen in einer Schleife
US6092184A (en) * 1995-12-28 2000-07-18 Intel Corporation Parallel processing of pipelined instructions having register dependencies
US5880983A (en) * 1996-03-25 1999-03-09 International Business Machines Corporation Floating point split multiply/add system which has infinite precision
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
WO1998006029A1 (en) * 1996-08-07 1998-02-12 Valery Yakovlevich Gorshtein Apparatus and methods for execution of computer instructions
US5845103A (en) * 1997-06-13 1998-12-01 Wisconsin Alumni Research Foundation Computer with dynamic instruction reuse
US6523055B1 (en) 1999-01-20 2003-02-18 Lsi Logic Corporation Circuit and method for multiplying and accumulating the sum of two products in a single cycle
US6636995B1 (en) 2000-07-13 2003-10-21 International Business Machines Corporation Method of automatic latch insertion for testing application specific integrated circuits
US7231510B1 (en) * 2001-11-13 2007-06-12 Verisilicon Holdings (Cayman Islands) Co. Ltd. Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof
US9871510B1 (en) 2016-08-24 2018-01-16 Power Integrations, Inc. Clamp for a hybrid switch
KR102425668B1 (ko) * 2017-02-23 2022-07-28 에이알엠 리미티드 데이터 처리장치에서의 곱셈-누적

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3697734A (en) * 1970-07-28 1972-10-10 Singer Co Digital computer utilizing a plurality of parallel asynchronous arithmetic units
JPS5166746A (ja) * 1974-12-06 1976-06-09 Fujitsu Ltd Naisekienzanshorikairo
US4075704A (en) * 1976-07-02 1978-02-21 Floating Point Systems, Inc. Floating point data processor for high speech operation
JPS5840214B2 (ja) * 1979-06-26 1983-09-03 株式会社東芝 計算機システム
JPS56147260A (en) * 1980-04-18 1981-11-16 Nec Corp Lsi for digital signal processing
EP0042452B1 (de) * 1980-06-24 1984-03-14 International Business Machines Corporation Signalprozessorrechneranordnung und Verfahren zum Betrieb der Anordnung
KR860001434B1 (ko) * 1980-11-21 1986-09-24 후지쑤 가부시끼가이샤 데이타 처리시 스템
JPS58181165A (ja) * 1982-04-16 1983-10-22 Hitachi Ltd ベクトル演算プロセツサ
JPS5999540A (ja) * 1982-11-29 1984-06-08 Toshiba Corp 浮動小数点演算装置
JPS59174974A (ja) * 1983-03-25 1984-10-03 Matsushita Electric Ind Co Ltd オ−バ−フロ−処理方法
US4766564A (en) * 1984-08-13 1988-08-23 International Business Machines Corporation Dual putaway/bypass busses for multiple arithmetic units

Also Published As

Publication number Publication date
US4683547A (en) 1987-07-28
EP0180048A2 (de) 1986-05-07
JPS61107431A (ja) 1986-05-26
EP0180048B1 (de) 1992-06-17
EP0180048A3 (en) 1988-06-22

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