DE3574077D1 - Process for forming diffusion regions in a semiconductor substrate - Google Patents

Process for forming diffusion regions in a semiconductor substrate

Info

Publication number
DE3574077D1
DE3574077D1 DE8585906019T DE3574077T DE3574077D1 DE 3574077 D1 DE3574077 D1 DE 3574077D1 DE 8585906019 T DE8585906019 T DE 8585906019T DE 3574077 T DE3574077 T DE 3574077T DE 3574077 D1 DE3574077 D1 DE 3574077D1
Authority
DE
Germany
Prior art keywords
semiconductor substrate
diffusion regions
forming diffusion
forming
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585906019T
Other languages
English (en)
Inventor
George Collins
Werner Metz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE3574077D1 publication Critical patent/DE3574077D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
DE8585906019T 1984-12-10 1985-11-25 Process for forming diffusion regions in a semiconductor substrate Expired DE3574077D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/680,034 US4666557A (en) 1984-12-10 1984-12-10 Method for forming channel stops in vertical semiconductor surfaces
PCT/US1985/002302 WO1986003620A2 (en) 1984-12-10 1985-11-25 Process for forming diffusion regions in a semiconductor substrate

Publications (1)

Publication Number Publication Date
DE3574077D1 true DE3574077D1 (en) 1989-12-07

Family

ID=24729383

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585906019T Expired DE3574077D1 (en) 1984-12-10 1985-11-25 Process for forming diffusion regions in a semiconductor substrate

Country Status (5)

Country Link
US (1) US4666557A (de)
EP (1) EP0204752B1 (de)
JP (1) JPH0628283B2 (de)
DE (1) DE3574077D1 (de)
WO (1) WO1986003620A2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0259629A1 (de) * 1986-08-19 1988-03-16 Siemens Aktiengesellschaft Verfahren zum Herstellen einer definierten Dotierung in den vertikalen Seitenwänden und den Böden von in Halbleitersubstrate eingebrachten Gräben
US4782036A (en) * 1986-08-29 1988-11-01 Siemens Aktiengesellschaft Process for producing a predetermined doping in side walls and bases of trenches etched into semiconductor substrates
JPH01147829A (ja) * 1987-12-04 1989-06-09 Toshiba Corp 半導体装置の製造方法
US5354710A (en) * 1988-01-14 1994-10-11 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices using an adsorption enhancement layer
US5057443A (en) * 1988-06-29 1991-10-15 Texas Instruments Incorporated Method for fabricating a trench bipolar transistor
IT1225625B (it) * 1988-11-03 1990-11-22 Sgs Thomson Microelectronics Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos.
US5008208A (en) * 1988-12-07 1991-04-16 Honeywell Inc. Method of making planarized, self-aligned bipolar integrated circuits
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device
JP2641781B2 (ja) * 1990-02-23 1997-08-20 シャープ株式会社 半導体素子分離領域の形成方法
JP2597022B2 (ja) * 1990-02-23 1997-04-02 シャープ株式会社 素子分離領域の形成方法
EP0445471A3 (en) * 1990-03-06 1994-10-26 Digital Equipment Corp Method of forming isolation trenches in a semiconductor substrate
EP0631305B1 (de) * 1993-06-23 1998-04-15 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Isolationsgrabens in einem Substrat für Smart-Power-Technologien
EP0635884A1 (de) * 1993-07-13 1995-01-25 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Grabens in einem Substrat und dessen Verwendung in der Smart-Power-Technologie
US5406515A (en) * 1993-12-01 1995-04-11 International Business Machines Corporation Method for fabricating low leakage substrate plate trench DRAM cells and devices formed thereby
DE4404757C2 (de) * 1994-02-15 1998-08-20 Siemens Ag Verfahren zur Herstellung eines einem Graben benachbarten Diffusionsgebietes in einem Substrat
KR0151051B1 (ko) * 1995-05-30 1998-12-01 김광호 반도체장치의 절연막 형성방법
TW304293B (en) * 1996-11-18 1997-05-01 United Microelectronics Corp Manufacturing method for shallow trench isolation
US5851900A (en) * 1997-04-28 1998-12-22 Mosel Vitelic Inc. Method of manufacturing a shallow trench isolation for a semiconductor device
US6069058A (en) * 1997-05-14 2000-05-30 United Semiconductor Corp. Shallow trench isolation for semiconductor devices
US6001684A (en) * 1997-06-04 1999-12-14 Siemens Aktiengesellschaft Method for forming a capacitor
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
TW589708B (en) * 2003-08-19 2004-06-01 Nanya Technology Corp Method for defining deep trench in substrate and multi-layer hard mask structure for defining the same
US20070080403A1 (en) * 2005-10-06 2007-04-12 David Litfin Low trigger voltage electrostatic discharge protection device
KR100769146B1 (ko) * 2006-08-17 2007-10-22 동부일렉트로닉스 주식회사 전기적 특성을 향상시키는 반도체 소자 및 그 제조 방법
US20090001481A1 (en) * 2007-06-26 2009-01-01 Ethan Harrison Cannon Digital circuits having additional capacitors for additional stability
US8129778B2 (en) * 2009-12-02 2012-03-06 Fairchild Semiconductor Corporation Semiconductor devices and methods for making the same
FR2978612B1 (fr) * 2011-07-27 2013-08-16 St Microelectronics Crolles 2 Procede de realisation d'une tranchee d'isolation dans un substrat semi-conducteur, et structure, en particulier capteur d'image cmos, obtenue par ledit procede
US9087872B2 (en) * 2011-07-27 2015-07-21 Stmicroelectronics (Crolles 2) Sas Method for forming an insulating trench in a semiconductor substrate and structure, especially CMOS image sensor, obtained by said method
US10910223B2 (en) * 2016-07-29 2021-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Doping through diffusion and epitaxy profile shaping
EP3349239B1 (de) * 2016-11-25 2020-04-08 Shindengen Electric Manufacturing Co., Ltd. Halbleiterbauelementherstellungsverfahren
CN110233130A (zh) * 2019-05-29 2019-09-13 长江存储科技有限责任公司 半导体结构、uhv器件及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5412791A (en) * 1977-06-29 1979-01-30 Tokyo Tokushu Densen Toryo Apparatus for measuring heat softening temperature of wire coating
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
JPS55127016A (en) * 1979-03-26 1980-10-01 Hitachi Ltd Manufacturing of semiconductor device
DE2951292A1 (de) * 1979-12-20 1981-07-02 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zum dotieren von siliciumkoerpern durch eindiffundieren von bor
US4353086A (en) * 1980-05-07 1982-10-05 Bell Telephone Laboratories, Incorporated Silicon integrated circuits
US4407058A (en) * 1981-05-22 1983-10-04 International Business Machines Corporation Method of making dense vertical FET's
US4466178A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics
US4466180A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping
US4379727A (en) * 1981-07-08 1983-04-12 International Business Machines Corporation Method of laser annealing of subsurface ion implanted regions
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer

Also Published As

Publication number Publication date
WO1986003620A3 (en) 1986-07-31
EP0204752B1 (de) 1989-11-02
JPS62501041A (ja) 1987-04-23
US4666557A (en) 1987-05-19
EP0204752A1 (de) 1986-12-17
WO1986003620A2 (en) 1986-06-19
JPH0628283B2 (ja) 1994-04-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL INC., DAYTON, OHIO, US

8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., 8910 LANDSBERG FIENER, J., PAT.-ANWAELTE, 8948 MINDELHEIM

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US