DE3573355D1 - Semiconductor package substrate and manufacturing process - Google Patents

Semiconductor package substrate and manufacturing process

Info

Publication number
DE3573355D1
DE3573355D1 DE8585105548T DE3573355T DE3573355D1 DE 3573355 D1 DE3573355 D1 DE 3573355D1 DE 8585105548 T DE8585105548 T DE 8585105548T DE 3573355 T DE3573355 T DE 3573355T DE 3573355 D1 DE3573355 D1 DE 3573355D1
Authority
DE
Germany
Prior art keywords
manufacturing process
semiconductor package
package substrate
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585105548T
Other languages
English (en)
Inventor
Anthony Francis Arnold
Arnold Friedri Schmeckenbecher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3573355D1 publication Critical patent/DE3573355D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/017—Glass ceramic coating, e.g. formed on inorganic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
DE8585105548T 1984-05-21 1985-05-07 Semiconductor package substrate and manufacturing process Expired DE3573355D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/612,296 US4521449A (en) 1984-05-21 1984-05-21 Process for forming a high density metallurgy system on a substrate and structure thereof

Publications (1)

Publication Number Publication Date
DE3573355D1 true DE3573355D1 (en) 1989-11-02

Family

ID=24452570

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585105548T Expired DE3573355D1 (en) 1984-05-21 1985-05-07 Semiconductor package substrate and manufacturing process

Country Status (4)

Country Link
US (1) US4521449A (de)
EP (1) EP0165427B1 (de)
JP (1) JPS60251693A (de)
DE (1) DE3573355D1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4645733A (en) * 1983-11-10 1987-02-24 Sullivan Donald F High resolution printed circuits formed in photopolymer pattern indentations overlaying printed wiring board substrates
US4756929A (en) * 1983-11-10 1988-07-12 Sullivan Donald F High density printing wiring
GB2214513B (en) * 1985-10-25 1990-02-28 Oxley Dev Co Ltd Semi-conductor package
JPS62136098A (ja) * 1985-12-09 1987-06-19 富士通株式会社 高密度配線基板
JPH0632355B2 (ja) * 1986-01-27 1994-04-27 株式会社日立製作所 セラミツク配線基板とその製造方法
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors
JPH0714105B2 (ja) * 1986-05-19 1995-02-15 日本電装株式会社 混成集積回路基板及びその製造方法
GB2197540B (en) * 1986-11-12 1991-04-17 Murata Manufacturing Co A circuit structure.
US4763403A (en) * 1986-12-16 1988-08-16 Eastman Kodak Company Method of making an electronic component
WO1988005959A1 (en) * 1987-02-04 1988-08-11 Coors Porcelain Company Ceramic substrate with conductively-filled vias and method for producing
US4942076A (en) * 1988-11-03 1990-07-17 Micro Substrates, Inc. Ceramic substrate with metal filled via holes for hybrid microcircuits and method of making the same
US4985601A (en) * 1989-05-02 1991-01-15 Hagner George R Circuit boards with recessed traces
US5254191A (en) * 1990-10-04 1993-10-19 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of ceramic bodies
DE9016266U1 (de) * 1990-11-29 1991-03-21 Siemens Nixdorf Informationssysteme AG, 4790 Paderborn Mehrlagenleiterplatte in Mikroverdrahtungstechnologie
JP3166251B2 (ja) * 1991-12-18 2001-05-14 株式会社村田製作所 セラミック多層電子部品の製造方法
JP2559977B2 (ja) * 1992-07-29 1996-12-04 インターナショナル・ビジネス・マシーンズ・コーポレイション バイアに係るクラックを除去する方法及び構造、並びに、半導体セラミックパッケージ基板。
US5342999A (en) * 1992-12-21 1994-08-30 Motorola, Inc. Apparatus for adapting semiconductor die pads and method therefor
US5406034A (en) * 1992-12-21 1995-04-11 Motorola, Inc. Circuit board having stepped vias
US5460921A (en) * 1993-09-08 1995-10-24 International Business Machines Corporation High density pattern template: materials and processes for the application of conductive pastes
US6251471B1 (en) * 1999-05-12 2001-06-26 University Of New Hampshire Surface trace electrical feedthru
JP4160901B2 (ja) * 2001-10-01 2008-10-08 ヘラエウス インコーポレイテッド マイクロエレクトロニクス用自己拘束型非焼結低温ガラスセラミックテープ及びその製法ならびに用途
US7714432B2 (en) * 2002-07-26 2010-05-11 Intel Corporation Ceramic/organic hybrid substrate
JP4150604B2 (ja) * 2003-01-29 2008-09-17 日立マクセル株式会社 半導体装置
US7332805B2 (en) * 2004-01-06 2008-02-19 International Business Machines Corporation Electronic package with improved current carrying capability and method of forming the same
WO2006067929A1 (ja) * 2004-12-20 2006-06-29 Murata Manufacturing Co., Ltd. 積層セラミック電子部品およびその製造方法
EP3301082B1 (de) * 2016-09-30 2024-09-18 Infineon Technologies AG Verfahren zur herstellung eines metall-keramik-substrats

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978248A (en) * 1970-12-18 1976-08-31 Hitachi, Ltd. Method for manufacturing composite sintered structure
US4109377A (en) * 1976-02-03 1978-08-29 International Business Machines Corporation Method for preparing a multilayer ceramic
US4245273A (en) * 1979-06-29 1981-01-13 International Business Machines Corporation Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices
US4322778A (en) * 1980-01-25 1982-03-30 International Business Machines Corp. High performance semiconductor package assembly
US4374457A (en) * 1980-08-04 1983-02-22 Wiech Raymond E Jr Method of fabricating complex micro-circuit boards and substrates
US4340618A (en) * 1981-03-20 1982-07-20 International Business Machines Corporation Process for forming refractory metal layers on ceramic substrate
EP0082216B1 (de) * 1981-12-23 1985-10-09 Ibm Deutschland Gmbh Mehrschichtiges, keramisches Substrat für integrierte Halbleiterschaltungen mit mehreren Metallisierungsebenen
US4442137A (en) * 1982-03-18 1984-04-10 International Business Machines Corporation Maskless coating of metallurgical features of a dielectric substrate

Also Published As

Publication number Publication date
EP0165427A2 (de) 1985-12-27
US4521449A (en) 1985-06-04
JPS60251693A (ja) 1985-12-12
JPH0235466B2 (de) 1990-08-10
EP0165427A3 (en) 1987-01-28
EP0165427B1 (de) 1989-09-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee