DE3543665A1 - INPUT CIRCUIT FOR CHARGED COUPLING ELEMENTS - Google Patents

Description

Input circuit for charge coupled devices

The invention includes a novel concept of a Input circuit for charge coupled devices (CCD). Such components are used in a variety of ways in microelectronics and optoelectronics, both in the form of individual lines and in flat lines Arrangements of combined lines.

Two types of input circuits are known in charge coupled devices (CCD). On the one hand the so-called electrical signal inputs and on the other hand reference charge generators. A typical representative of the first group uses the "fill and spill ¹ *" method of input circuitry. A diode area adjoins the first electrode of a CCD shift register. A direct voltage is applied to this first electrode. The second electrode is the The electrical signal is applied to it, to which proportional charge packets are to be generated, which are then shifted from cell to cell in the following CCD register, the third, fourth and all other electrodes are already register electrodes in the rhythm of the clock frequency. For operation, a pulse voltage is applied to the input diode area, the frequency of which is equal to the clock frequency and by means of which the diode area is brought from a sufficiently high blocking level to a defined lower blocking voltage for a short period of time.

semi only a "short time period" because after the "padding" (fill) of the potential well below the second electrode (input electrode), which happens during the small reverse voltage, enough time to "flow back" (spill) of the excess charge from the potential well must be present under the second electrode via the potential barrier under the first electrode in the input diode area before the charge from the potential well is transferred to the following register cell. This "back flow" can only take place if the input diode area is at the sufficiently high blocking level.

A typical representative of the second group is a so-called white value generator, as it is used in optical CCD sensor lines is used (e.g. CCD 133 from Fairchild and L 133 from VEB WF). The white level generator comes with the one Impulse controlled, which transfers the optically generated signal charges from the sensors to the CCD shift register triggers. This pulse is applied to the electrodes of the white value generator, while that in turn is applied to the first electrode adjacent diode area is kept at a constant DC voltage level.

Usually a CCD register is only part of an input circuit one of the two groups. In the DD patent application WP H 01 L / 2 53669/1 a complex input circuit proposed with both an electrical signal input and a generation of white signals is possible. This enables the simultaneous processing of electrical and optical signals.

For the function of the electrical signal input, the special pulse voltage explained above is used at the input diode area required, while the white value generation takes place via the transfer pulse mentioned.

In the case of the known white value generators, the "flowing back" of excess charge, only the duration of one clock edge of the transfer pulse is available. There-

This means that the size of the reference charge generated is not determined too precisely in the case of very steep pulses.

The aim of the invention was that which adhered to the prior art To eliminate deficiency.

The invention was based on the object of constructing an input circuit for charge-coupled devices, which are used both for electrical signal input and for generating reference charges can, no special pulse voltage required and reference charges generated with great accuracy.

To solve this problem, an input circuit is constructed that uses a novel concept of charge input realized. Furthermore, in this circuit a spatial separation of the areas, which are to be "filled in" serve as a potential well with charge, reached by areas that are intended for the drainage of excess charge

The essence of the invention is explained on the assumption that that the CCD shift register is a two-phase register (or four-phase register) in which the clock pulse sequence is applied to one phase while the other phase is held at a DC voltage level. This is at the same time the operating mode of a single-phase register is also recorded. Should the inventive idea for a three-phase register as well as for a two-phase register (or four-phase register) in which clock pulse trains are applied to both phases are used, then result for the control voltages of the individual electrodes of the input circuit have certain level shifts that are not more specific to the person skilled in the art need to be explained.

According to the invention, the input circuit is as follows constructed:

At the beginning of the CCD shift register, only separated from it by a control electrode with the control area below it, there is a signal area which is preferably controlled by a signal electrode in which a potential well is formed. If a signal electrode is present, the depth of this trough is proportional to the voltage across it. A drainage area, which can be controlled by a drainage electrode, is positioned between the signal area and a diode area and has approximately the same width as the signal area (width is understood to be the geometric dimension perpendicular to the transport direction of the CCD register). At right angles to the transport direction of the CCD register, the signal area borders on an inflow area, which can be controlled by an inflow electrode, which in turn is adjoined by a scoop area with a scoop electrode located above. This latter is separated by a Obertragungsgebiet with overlying transfer electrode of a diode region, said diode region is preferably electrically connected to that which is adjacent to the drain region. If the electrodes mentioned are classified according to the terms customary for two-phase CCDs, then the signal and scoop electrodes count as storage electrodes, ie potential wells form below them, in which charges can be stored. The outflow, inflow, transfer and control electrodes are then transfer electrodes, ie potential barriers are formed under them in relation to the storage areas, the signal charges only pass through these areas during the transfer from one storage area to the other or during the transfer between diode areas and storage areas the first CCD register electrode adjoining the control electrode is a storage electrode on which the clock pulse train is located.

The electrical signal input is implemented according to the invention as follows j

The transmission, scoop and control electrodes are fed with the clock pulse sequence required for the CCD register. If the inflow area is controlled by an electrode, this inflow electrode is supplied with a direct voltage; for this purpose it is preferably connected to the second phase of the CCD register, which is at a direct voltage level. The two diode regions, which are preferably connected to one another, are polarized in the reverse direction with a direct voltage of sufficient magnitude, for which further explanations are given below. The electrical input signal is normally applied to the signal electrode. If the drainage area is controlled by an electrode, this drainage electrode is kept at a DC voltage level, for which purpose the DC voltage controlling the second phase of the CCD register is preferably used. Operation is, however, with reversed feeds for _(tliese two electrodes is possible, that the input signal is applied to the drain electrode, while the signal electrode is supplied with said DC voltage.

The reverse voltage at the adjacent to the transfer electrode The diode area is chosen to be so large that when the clock pulse sequence is high, the potential barrier is below the Transfer electrode is lowered so far that charges (with regard to the substrate, they are minority carriers) from the diode region unimpeded into the potential well below the Can flow scoop electrode. The potential level in the diode area However, it must in any case be lower than the extreme value of the potential in completely minority carriers impoverished river basin, so that during the high-level the Charge carriers originating from the diode area can only flow into the trough under the scoop electrode.

At the next low level of the clock pulse sequence, the potential raised under transfer and scoop electrode, so far that the potential well below the

Scoop electrode is still shallower even if this area is completely depleted of minority charge carriers compared to the low point of the potential in the inflow area. All minority charge carriers thus flow during the low level from the potential well under the scoop electrode via the inflow area into the potential well under the signal electrode. Under the also at low level lying control electrode there is a potential barrier, so that a charge transfer into the following

XQ CCD register is disabled. The potential barrier of the drainage area is much smaller than that of the control area. All excess charge carriers from the signal area flow through the barrier of the drainage area into the adjacent diode area until the potential in the signal area reaches the barrier value in the drainage area. In proportion to the size of the electrical signal applied to the signal electrode, a charge packet remains in the signal area, which flows into the CCD register at the next high level of the clock pulse train.

This is because the control electrode and the first CCD register storage electrode are supplied with the clock voltage. Through this the potential barrier under the control electrode is broken down, and the charge carriers can be removed from the signal area (under the signal electrode) flow unhindered into the potential well under the first CCD register storage electrode » During this high level, charge carriers flow again from the diode area via that of the transfer electrode controlled transfer area in the potential well under the scoop electrode, and the entire described up to this point The process of entering the charge is repeated.

The fact that the drainage area by the invention Construction approximately the width of the signal area, it is ensured that the potential in the signal area through The discharge of the excess charge carriers reaches the value determined by the potential barrier of the discharge area. The size of the charge packets remaining in the signal area and then flowing into the CCD register can thus precisely defined by the voltage applied to the signal electrode. It should also be pointed out

sen that in the described operating mode according to the invention the duration of an entire low »or high phase of the clock pulse for filling or draining Available. With the well-known fill and spill method filling and backflow must be handled during the sole duration of the low phase, which is the Precision of the charge input, especially at high clock frequencies, is worsened compared to the method according to the invention.

A particular advantage of the method according to the invention is that there is no special pulse voltage for the input circuit is required · The proposed input circuit uses the one provided for the CCD register iBipulse voltage, the input diodes are on an equal tension.

The use of the input part to enter a reference charge (for example a "white value") in the case of optical CCD sensor lines occurs according to the invention as follows:

The transmission, scoop and control electrodes are with the transfer pulses required to realize the charge transport between the sensor cell and the CCD register. The remaining electrodes are supplied in the same way as for the electrical signal input. The one at the signal electrode applied voltage value determines the size of the reference charge. The transfer pulse train consists of short ones High phases that occur during the high phase of a clock pulse, shorter or the same in duration are the high phase of a clock pulse. The low level lasts during the entire light integration phase of the sensor line of the transfer pulse.

In principle, the generation of the reference charge takes place in the same way as described above for the electrical signal input. The only difference is that it is the result of a

The charge packet generated by the transfer pulse is not immediately passed on to the CCD register, but rather via the light integration phase and thus the low-level phase of the transfer pulse train is stored away in the signal area and only is transferred to the CCD register with the next transfer pulse.

The reference charge does not change its value, since all additional charge carriers such as For example, the thermally generated, constantly flowing away via the drainage area into the input diode.

As described, the input arrangement according to the invention can by switching the supply for the transfer, scoop and control electrode to either electrical signal input or for reference charge generation be used.

In a special embodiment of the invention, electrical signal input and reference charge generation are possible at the same time. In addition to the input arrangement described so far, a further, similar arrangement is used. The arrangement described so far and positioned in front of the first CCD register electrode is preferably used in this case for electrical signal input. The additional arrangement is attached to the CCD register laterally, preferably serves the reference charge extraction and the generated charge is not necessarily transferred to the first CCD register storage electrode. According to the design, the generated charge can take place in the second, third or even further positioned storage electrode of the CCD register. Axis "of the CCD register, now together with the other areas of the input circuit, are attached perpendicularly away from the" Achee ". Due to this arrangement, the drainage

- A
is no longer as wide as in the basic arrangement. When a reference level is obtained with the transfer pulse (white value generation), the discharge phase of excess charge is very long in terms of time, namely the entire light integration phase. This ensures a high level of accuracy of the reference level (white value) despite the narrow drainage area.

The lateral arrangement may be mounted several times * For a white reference it is recommended that two white values in succession through the CCD registers to push · It can thereby be reduced in height at the end of the register, the first white balance due to transfer losses, while the second quasi unadulterated and thus reaches the line output as the actual reference level.

For further details of the additional, laterally attached reference level arrangement, refer to the corresponding exemplary embodiment referenced.

The invention will be explained in more detail using an exemplary embodiment with reference to the drawings.

In the drawings show:

Fig. 1: Schematic structure of the invention

Input circuit

Cross section along the line AA * from FIG. 1

Potential diagrams

Cross section along the line BB 'from FIG. 1

Potential diagrams

Layout drawing of a practical embodiment of the input circuit according to FIGS. 1-3

Layout drawing of an embodiment of the input circuit for double reference pe

gel input

Fig. 2a: Fig. 2b, c: 25 fig 3a: Fig. 3b, c: Fig. 4t Fig. 5:

The invention is applicable to both surface CCD's and can be used for buried channel CCDs. In the exemplary embodiment is powered by a two-phase BCCD with a p-type Starting out substrate · Of course, the invention can also be implemented with η-conductive substrates.

The schematic structure of the input circuit according to the invention is shown in FIG. 1. The potentials in all areas are controlled by electrodes placed above them. The symbols are: 18 transfer electrode, 19 scoop electrode, 20 inflow electrode, 21 outflow electrode, 22 signal electrode, 23 control electrode, first BCCD register storage electrode, 25 transfer electrode of the second register cell, 26 storage electrode of the second register cell, 27 and 28 transfer and storage electrode of the third register cell , 29 and 30 transfer and storage electrode of the fourth register cell, transfer electrode of the fifth register cell. The diodes adjoining the transmission electrode 18 and the drain electrode 21 are shown as a common area 17 which is _{supplied with the direct voltage U 1} via the line 10. The electrodes 24, 27, 28 and 31 are fed with the clock pulse train U ₃ via the clock pulse line 13. The electrodes 25, 26, 29 and 30 are connected to the direct voltage U. via the direct voltage line 14. The inflow electrode 20 is fed with the direct voltage U _g and the outflow electrode 21 with the direct voltage U ₇ . _{The DC voltage U 4} required for the BCCD register can preferably be used for U _ß and U-. _{The voltage U 5} supplied to the signal electrode 22 via the line 11 determines the size of the charge packet generated. The transmission, scoop and control electrodes (18, 19 and 23) are supplied _{with the input pulse voltage U 2 via the input pulse voltage line 12.} The clock pulse sequence U, is used for U ₂ when an electrical signal is input, and for when a reference level is obtained for

"to ·

optical sensor lines (, white value generation) is used as U _2, the transfer pulse train.

In Fig. 2a is a vertical section along the line AA ' shown. The potential curves are shown in FIGS. 2b and 2c recorded under the signal electrode 22 for the decisive stages in the generation of the charge packet. The buried-channel storage areas are 15, which generate potential barriers Dopings with 16, the substrate with 32, the gate insulator with 33 and the field insulator denoted by 34.

The n ^{+ region} 17 is held at the blocking potential 36 (FIG. 2b). In the channel stopper region 38 under the field insulator 34, the potential reaches the substrate value 35. If the high level of U _{2 is} at the electrodes 13 and 19, electrons flow from the n ^{+ region} 17 in the direction of arrow 42 into the potential well 46 under the scoop electrode 19 until the potential under the electrodes 18 and 19 reaches the value 36. In the area under the transfer electrode 18 that is completely depleted of electrons, the potential would reach the value 37. At the subsequent low level of U ₂ (Fig. 2c), the charge flows under the scoop electrode 19 in the direction of arrow 44 over the potential barrier 39, which is maintained under the inflow electrode 20, into the potential well 40 under the signal electrode 22 (FIG. 2b) was "overfilled" with electrons, a small part of the charge flows back ^{into the n + region 17 in the direction of arrow 43, depending on the steepness of the high-low pulse edge.} In the areas under the electrodes 18 and 19 that are ultimately completely depleted of electrons, the potential takes the course 48 and 49. The capacity of the potential well 40 is determined by its relative depth to the potential barrier 41 under the drainage electrode 21. All excess electrons flow in the direction of the arrow 45 into the n * region 17 until the potential below the signal electrode 22 reaches the barrier value 41.

In Fig. 3a a vertical section along the line BB 'is shown, in Fig. 3b and 3c are the potential curves for the decisive stages in the input of the charge packet located under the signal electrode 22 recorded in the BCCD register.

FIG. 3b corresponds to the same moment in time for which FIG. 2c was drawn. The potential barrier 48 is built up under the control electrode 23 because the pulse voltage U ₂ is currently at its low level. If the input circuit were used for the electrical signal input, U ₂ would be equal to U, and this would result under the electrodes 24, 27 and 28 (with complete depletion of electrons) the potential curves 50, 52 and again 50. Under the electrodes fed by the direct voltage U. (with complete depletion of electrons) the potential 39 is established in the transfer area and the potential 51 in the storage area. For the case of white value generation, FIG. 3b shows a moment during the light integration phase in which the clock pulse sequence U- just reaches the low level. For U ₂ , which would be the transfer pulse sequence for white level generation, the low level then prevails over the entire light integration phase. Below the signal electrode 22, the potential changes to the value 47 as a result of the stored charge.

Fig. 3c shows the moment in which the pulse voltage U ₂ assumes the high level. _{The high phases at U 2} and U ₃ coincide in time with both electrical signal input and reference level acquisition. In the event of a depletion of electrons, the potentials 53 and 54 are established below the electrodes 27 and 28. The charge localized under the signal electrode 22 flows in the direction of arrow 56 over the lowered barrier 37 into the trough 54, as a result of which the potential under the first CCD register storage electrode 24 increases to the value 55. Simultaneously with the process shown in FIG. 3c, electrons again flow from the n ^{+ region} 17 into the potential well 46 (see FIG. 2b), and the entire process described is repeated.

4 shows the layout of the most important levels of a practical implementation of the input circuit according to FIGS. 1, 2 and 3. The storage electrodes 24, 26, 28 of the BCCD register have the dimensions 10 × 30 μm. The individual lines mean: 60 border between field insulator (plus channel stopper area) and gate insulator, 61 electrodes of the first electrode level (e.g. first poly-Si layer), 62 electrodes of the second electrode level (e.g. second poly-Si layer), 63 interconnect level (e.g. Al), 64 contact windows. The inflow electrode 20 and the outflow electrode 21 are connected directly to the electrode 25 in FIG. 4 and thus connected to the direct voltage U ₄ . The same applies to the function of the circuit from FIG. 4 as explained with reference to FIGS. 1, 2 and 3.

In Fig. 5 the layout of the most important levels of an embodiment of the input circuit is shown, which is attached to the side of the CCD register and is preferably used to obtain the reference level. Fig. 5 is a section from the initial part of a typical BCCD sensor line. The transport directions of the two BCCD registers, indicated above and below in FIG. 5, are symbolized by the arrows 80 and S1. The transfer electrodes 69, 73 and 77, like the storage electrodes 70, 74 and 78, are supplied _{by the clock pulse sequence U 3.} The transfer electrodes 71 and 75 and the storage electrodes 72 and 76 are fed by the direct voltage U ₄ . The inflow, outflow and signal electrodes 20, 21 and 22 are also connected to U _{4 »}

Two white values are entered one after the other into each of the two BCCD registers, and the transfer pulse sequence becomes U « taken. As can be seen from Fig. 5, the drainage electrode 21 can no longer be made so wide, as is possible with the basic version in FIG. 1. Because the low-level phase of the transfer pulse and thus the drainage time excess charge is very long, namely the duration of the entire light integration phase, the White values generated with great accuracy.

_{The pulse voltage U 1 is} fed to the electrodes 12 and 19 via the contact windows 82 and 84, the η region 17 receives the direct voltage U 1 through the contact window 83. The corresponding Al tracks are not shown in FIG. 5 for the sake of clarity. The corner of the channel stopper area marked 86 protrudes under the signal electrode 22, so that if the planes are shifted relative to each other due to dusting and preparation tolerances, a change in the effective signal electrode area is compensated for by the channel stopper area 85 also protruding under the electrode 22 will.

... Otherwise, the same reference numbers, the function of the arrangement of FIG are shown in Figure 5 registered, as shown in Figures 1 to 4. For 5 applies the 1 to 3 with reference to FIG he -. Enlightened "_.

List of the reference symbols used

10 DC voltage line

11 Signal voltage line

12 input pulse voltage line

13 clock pulse line

14 DC voltage line

15 buried channel storage areas

16 dopings that create potential barriers

17 n ^{+ region}

18 transmission electrode

19 Scoop Electrode

20 inflow electrode

21 drainage electrode

22 signal electrode

23 control electrode

24 first BCCD register storage electrode

25 Transfer electrode of the second register cell

26 storage electrode of the second register cell

27 Transfer electrode of the third register cell

28 storage electrode of the third register cell

29 transfer _{electrode) in the fourth register: tell}

30 storage electrode I.

31 Transfer electrode of the fifth register cell

32 substrate

33 gate insulator

34 field isolator

35 substrate potential

36 blocking potential

37 potential

38 Channel stopper area

39 Potential barrier

40 potential well

41 Potential barrier

42 Direction of flow of electrons

43 Direction of flow of electrons

44 Direction of flow of electrons

45 Direction of flow of electrons

46 potential well

47 potential value

48 Potential curve

49 Potential curve

50 potential curve

51 Potential curve

52 Potential curve

53 Potential curve

54 Potential well

55 potential value

56 Direction of flow of electrons

60 Boundary between field and gate insulator

61 electrodes of the first electrode level

62 electrodes of the second electrode level

63 channel level

64 Contact Window

69 transfer electrode

70 storage electrode

71 transfer electrode

72 storage electrode

73 transfer electrode

74 storage electrode

75 transfer electrode

76 storage electrode

77 transfer electrode

78 storage electrode

80 Direction of transport of the BCCQ register

81 Transport direction of the BCCD register

82 Contact Window

83 Contact Window

84 Contact Window

85 channel stopper area

86 Corner of the channel stopper area

U ₁ DC voltage

U "input pulse voltage

U ₃ clock pulse train

U ^ DC voltage

U_ voltage

υ, DC voltage

U- DC voltage

Claims (4)

3543-65 claims 1. Input circuit for charge-coupled devices, characterized in that a first reverse-polarized diode area is followed in series by a transmission area, a scoop area, an inflow area and a signal area, and that this ßiQ- nal area is followed by two more Areas, namely a drainage area and a control area, the drainage area separating the signal area from a second reverse-biased diode area, and that the control area is followed by a CCD shift register, which in turn begins with a storage area, and that the transmission area, the The scoop area and the control area controlling electrodes are connected to the same input pulse voltage, and that the first and second diode areas are preferably connected to one another, and that if the inflow area, the drainage area and the signal area are controlled by electrodes, these (electrodes) are preferably connected to direct voltages are connected, and that to implement an electrical signal input, the input pulse voltage line with that clock pulse voltage line of the CCD shift register, which the storage area following the control area chergebiet is controlled, connected, and that for realizing a reference level input the input pulse voltage line is connected to the transfer pulse line of the CCD sensor arrangement. 2. input circuit for charge coupled devices according to claim 1, characterized in that the control, Signal and drainage areas are arranged in the extended axis of the CCD register, with the drainage area approximately the same width as the signal area, while the transmission, scooping and inflow areas are arranged to the side of the CCD register. 3, charge coupled device input circuit according to claim 1 and 2, characterized in that for a 2-phase CCD, in which a phase with a Clock pulse train and the other phase are fed with a DC voltage, the inflow and outflow area controlling electrodes connected to the DC voltage line of the CCD shift register are. 4. input circuit for charge coupled devices according to claim 1 to 3, characterized in that for Realization of a double reference level input, the entire circuit is arranged to the side of the CCD register and is carried out in the special construction of FIG. 4 — Seirrein "tent: firiungön