CA1096042A - Introducing signal to charge-coupled circuit - Google Patents
Introducing signal to charge-coupled circuitInfo
- Publication number
- CA1096042A CA1096042A CA194,315A CA194315A CA1096042A CA 1096042 A CA1096042 A CA 1096042A CA 194315 A CA194315 A CA 194315A CA 1096042 A CA1096042 A CA 1096042A
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- 239000000758 substrate Substances 0.000 claims description 32
- 239000002800 charge carrier Substances 0.000 claims description 27
- 238000005036 potential barrier Methods 0.000 claims description 10
- 239000000969 carrier Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 claims 2
- 230000003334 potential effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 description 11
- 230000008859 change Effects 0.000 description 7
- 238000005192 partition Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 230000000644 propagated effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76808—Input structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76866—Surface Channel CCD
- H01L29/76875—Two-Phase CCD
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
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Abstract
Abstract The first potential well of a charge-coupled device (CCD) register is initially filled from a source diffusion and then the effective depth of this well is reduced and the excess charge removed. The depth reduction and charge removal may be concurrently accomplished by changing the relative potential between the source diffusion and the electrode or electrodes producing the first potential well in a sense to cause this diffusion to operate as a drain for the excess charge. The charge remaining in the first potential well is relatively noise free, that is, it is at a predictable and reproducible level.
Description
RCA 67,168 ~L096~
The input circuit to a charge-coupled register known to applicant is illustrated in FIGURE 1. Details of this circuit and a number of other input circuits may be found in copending Canadian application Serial No. 129,812 for "Charge Coupled Circuits" filed December 9, 1971 by the present inventor and assigned to the same assignee as the present application.
In the operation of a circuit such as shown in FIGURE 1, the source diffusion S is slightly reverse biased and operates as a source of minority carr.iers (holes in the case of the N type silicon substrate illustrated). The charge may be introduced to the surface of the substrate beneath the gate electrode G2 by applying a negative p1l1se produced by source 10 to the first gate electrode Gl. This pulse causes a conduct~on channel to extend from the source diffusion S to the region beneath the electrode G2. If this electrode is placed at a suitable negative potential, the minority charge carriers ~`
travel from the source diffusion to the potential well present under gate G2. These charges subsequently may be shifted along the register by the three phase voltages applied to the electrodes. The transfer process is discussed in detail in the copending application.
It has been found during the several years that charge-coupled circuits have been known, that the amoun~ of charge signal introduced into the first potential well is not accurately predictable, even though the various voltages employed are accurately controlled and the duration of the
The input circuit to a charge-coupled register known to applicant is illustrated in FIGURE 1. Details of this circuit and a number of other input circuits may be found in copending Canadian application Serial No. 129,812 for "Charge Coupled Circuits" filed December 9, 1971 by the present inventor and assigned to the same assignee as the present application.
In the operation of a circuit such as shown in FIGURE 1, the source diffusion S is slightly reverse biased and operates as a source of minority carr.iers (holes in the case of the N type silicon substrate illustrated). The charge may be introduced to the surface of the substrate beneath the gate electrode G2 by applying a negative p1l1se produced by source 10 to the first gate electrode Gl. This pulse causes a conduct~on channel to extend from the source diffusion S to the region beneath the electrode G2. If this electrode is placed at a suitable negative potential, the minority charge carriers ~`
travel from the source diffusion to the potential well present under gate G2. These charges subsequently may be shifted along the register by the three phase voltages applied to the electrodes. The transfer process is discussed in detail in the copending application.
It has been found during the several years that charge-coupled circuits have been known, that the amoun~ of charge signal introduced into the first potential well is not accurately predictable, even though the various voltages employed are accurately controlled and the duration of the
-2-RCA 67,l68 ~O~
l negative pulse produced by source l0 is accurately controlled.
Such random variations in the amount of charge introduced into the first potential well is defined here as noise due to electrically introduced input signal.
Other sources of noise in charge-coupled devices are the noise due to optically introduced signal, noise nssociated with the thermally generated background charge, and transfer noise due to incomplete transfer of charge and charge trapping by the fast surface states. These are discussed in J. E. Carnes and W. F. Kosonocky, "Noise Sources in Charge-Coupled Devices", RCA Review Vol. 33, p. 327, June 1~72. The present applic~tion deals with none of these but rather only with the method and apparatus for the selective noise-free electrical introduction of charge into the input circuit of a charge-coupled device circuit.
The circuit of FI~URE 1 ma~ be operated in a number of different ways. In one, the nega1;ive pulse produced at lO, which may be thought as the input signal Vin, is of relatively low amplitude. This creates a relatively high impedance conduction channel and in this condition, the source diffusion S operates as a constant current source.
(It simulates a source of high internal impedance). When operating in this way, the charge carriers flowing through ` the conduction channel during the time the input signal is relatively negative are emitted from the source in random ` fnshion and introduce what is known as "shot noise". What -~ this means, in a somewhat qualitative way, is that even though gate electrode Gl may be kept on for a very accurately mensured time interval and may be maintained at a very well defined potential, there is an uncertainty as to the precise RCA 67,168 1 number of charge carriers which will pass through the conduction channel formed beneath the gate electrode Gl and will accumulate in the first potential well (the potential well beneath electrode G2).
In an effort to overcome the problem above, the amplitude of the input signal Vin may be increased to make the conduction channel impedance very low thus filling the potential well to the level of the source potential. A
theory which has been developed indicates that this does indeed eliminate shot noise. Notwithstanding such elimina--tion of shot noise, it is still found that the charge accum-ulated in the first potential well is not accurately predictable. The reason, it is thought, is that when the ~ate electrode Gl is turned off,that is when the input signal Vi11 groes from its relntively negative to its relatively positive valùe, the relatively large number of carriers present in the conduction channel produced bv gate Gl must flow somewhere. It is thought that some of these carriers, rather than returning to the source electrode S, instead return to the first potential well (the well beneath electrode G2). The number of such charge carriers which end up in the first potential well is not accurately pre-dictable and this uncertainty in the level to which the first potential well is filled can be considered to be noise, which for purposes of this discussion will be termed "partition noise".
In the second method discussed above there is also a second source of noise. This noise is known as capacitive noise and is proportional to the s~quare root of .. .
capncitance associated with the first potential well (this ` ls discussed in the RCA Review article above).
RCA 67,168 ~96~2 1 In a number of embodiments of the inven-tion described in the copending application above~ the source electrode is pulsed. However, the noise problems remain the same. The operation is such that even when the source is pulsed, it is always attempted to fill the first potential well to some predetermined level proportioned to the magnitud~ and duration of the voltage employed for pulsing. In all of these embodiments, the source electrode is either operated as a constant current source with the accompanying shot noise or with low conduction channel impedance which results in the introduction of partition noise when the conduction channel collapses.
In the various embodiments of the present invention, the first potential well of a charge-coupled circuit is initially filled to at least a given depth, then the depth of the well is effectively lowered to a value defined by the difference between two surface potentials, to remove a portion of the charge formerly present in the well. As will be pointed out in more detail below, establishing a charge signal in this way is relatively noise free in the sense that the charge remaining in the first potential well is accurately predictable and reproducible.
In more detail, in one form of the present invention, the first potential well is beneath a second electrode means and this well is filled from a region in the substrate of different conductivity type than the substrate, and there is a first electrode means between this region and the second electrode means. The region is always maintained at a fixed potential. The potential well is filled with charge from this region and is partially emptied of charge by raising the .
RCA 67,168 ~964~42 1 potentials of -the first and second electrodes ln unison while the source reyion is at a fixed potential.
In a second form of the invention, the first and second electrode means are disconnected from the multiple phase voltages which are employed to propagate the signal charge accumulated in the potential well beneath the second electrode.
The invention is illustrated in the drawing of which:
FIGURE 1 is a section through the input circuit of a charge-coupled register known to applicant;
FIGURE 2 is a section through a charge-coupled register operated in accordance with one orm of the present invention;
FIGUR~ 3 is a drawing of surface potentials :, . ,~
/~
,/
~.
-5a-~9~42 RC~ 67,168 1 present at the semiconductor substrate of the device of FIGURE 2 during various time intervals;
FIGURE 4 is a section through the input circuit to a charge-coupled circuit operated in accordance with another form of the present invention;
FIGURE 5 is a drawing of surface potentials to help explain the operation of the circuit of FIGURE 4;
FIGURE 6 is a drawing of waveforms employed to operate the circuit of FIGURE 4; ~
FIGURE 7 is a section through an input circuit operated in accordance with another form of +he present invention;
FIGURE 8 is a drawing of surface potentials present in the circuit of FIGURE 7;
lS FIGURE 9 is a clrawing of waveforms employed in the operatio~ of the circuit of FIGU~E 7; and FIGURE 10 is a section through an lnput circuit operated in accordance with another form of the present invention.
Tbe structure of the circuit of FIGURE 2 is very similar to that of FIGURE 1. However, the source S, rather than being operated at a fixed potential, is driven by a voltage V6 produced by source 20. The gate electrode Gl is operated at a fixed potential Vl. The gate electrode G2 is also operated at a fixed potential V2, where V2 is more negative than Vl. The gate electrode G3 is connected to .
a voltage source 22 which applies a negat~ V9 pulse V3 to this electrode.
The operation of the circuit may be understood by referring to FIGURE 3. The surface potentlal profiles shown ~g6~42 RCA 67,168 l represent the surface potentials existing at the source S and the various gates, the potential lines being aligned with the structures which produce these surface potentials.
At time t1 (surface potential profile a of FIGURE
l negative pulse produced by source l0 is accurately controlled.
Such random variations in the amount of charge introduced into the first potential well is defined here as noise due to electrically introduced input signal.
Other sources of noise in charge-coupled devices are the noise due to optically introduced signal, noise nssociated with the thermally generated background charge, and transfer noise due to incomplete transfer of charge and charge trapping by the fast surface states. These are discussed in J. E. Carnes and W. F. Kosonocky, "Noise Sources in Charge-Coupled Devices", RCA Review Vol. 33, p. 327, June 1~72. The present applic~tion deals with none of these but rather only with the method and apparatus for the selective noise-free electrical introduction of charge into the input circuit of a charge-coupled device circuit.
The circuit of FI~URE 1 ma~ be operated in a number of different ways. In one, the nega1;ive pulse produced at lO, which may be thought as the input signal Vin, is of relatively low amplitude. This creates a relatively high impedance conduction channel and in this condition, the source diffusion S operates as a constant current source.
(It simulates a source of high internal impedance). When operating in this way, the charge carriers flowing through ` the conduction channel during the time the input signal is relatively negative are emitted from the source in random ` fnshion and introduce what is known as "shot noise". What -~ this means, in a somewhat qualitative way, is that even though gate electrode Gl may be kept on for a very accurately mensured time interval and may be maintained at a very well defined potential, there is an uncertainty as to the precise RCA 67,168 1 number of charge carriers which will pass through the conduction channel formed beneath the gate electrode Gl and will accumulate in the first potential well (the potential well beneath electrode G2).
In an effort to overcome the problem above, the amplitude of the input signal Vin may be increased to make the conduction channel impedance very low thus filling the potential well to the level of the source potential. A
theory which has been developed indicates that this does indeed eliminate shot noise. Notwithstanding such elimina--tion of shot noise, it is still found that the charge accum-ulated in the first potential well is not accurately predictable. The reason, it is thought, is that when the ~ate electrode Gl is turned off,that is when the input signal Vi11 groes from its relntively negative to its relatively positive valùe, the relatively large number of carriers present in the conduction channel produced bv gate Gl must flow somewhere. It is thought that some of these carriers, rather than returning to the source electrode S, instead return to the first potential well (the well beneath electrode G2). The number of such charge carriers which end up in the first potential well is not accurately pre-dictable and this uncertainty in the level to which the first potential well is filled can be considered to be noise, which for purposes of this discussion will be termed "partition noise".
In the second method discussed above there is also a second source of noise. This noise is known as capacitive noise and is proportional to the s~quare root of .. .
capncitance associated with the first potential well (this ` ls discussed in the RCA Review article above).
RCA 67,168 ~96~2 1 In a number of embodiments of the inven-tion described in the copending application above~ the source electrode is pulsed. However, the noise problems remain the same. The operation is such that even when the source is pulsed, it is always attempted to fill the first potential well to some predetermined level proportioned to the magnitud~ and duration of the voltage employed for pulsing. In all of these embodiments, the source electrode is either operated as a constant current source with the accompanying shot noise or with low conduction channel impedance which results in the introduction of partition noise when the conduction channel collapses.
In the various embodiments of the present invention, the first potential well of a charge-coupled circuit is initially filled to at least a given depth, then the depth of the well is effectively lowered to a value defined by the difference between two surface potentials, to remove a portion of the charge formerly present in the well. As will be pointed out in more detail below, establishing a charge signal in this way is relatively noise free in the sense that the charge remaining in the first potential well is accurately predictable and reproducible.
In more detail, in one form of the present invention, the first potential well is beneath a second electrode means and this well is filled from a region in the substrate of different conductivity type than the substrate, and there is a first electrode means between this region and the second electrode means. The region is always maintained at a fixed potential. The potential well is filled with charge from this region and is partially emptied of charge by raising the .
RCA 67,168 ~964~42 1 potentials of -the first and second electrodes ln unison while the source reyion is at a fixed potential.
In a second form of the invention, the first and second electrode means are disconnected from the multiple phase voltages which are employed to propagate the signal charge accumulated in the potential well beneath the second electrode.
The invention is illustrated in the drawing of which:
FIGURE 1 is a section through the input circuit of a charge-coupled register known to applicant;
FIGURE 2 is a section through a charge-coupled register operated in accordance with one orm of the present invention;
FIGUR~ 3 is a drawing of surface potentials :, . ,~
/~
,/
~.
-5a-~9~42 RC~ 67,168 1 present at the semiconductor substrate of the device of FIGURE 2 during various time intervals;
FIGURE 4 is a section through the input circuit to a charge-coupled circuit operated in accordance with another form of the present invention;
FIGURE 5 is a drawing of surface potentials to help explain the operation of the circuit of FIGURE 4;
FIGURE 6 is a drawing of waveforms employed to operate the circuit of FIGURE 4; ~
FIGURE 7 is a section through an input circuit operated in accordance with another form of +he present invention;
FIGURE 8 is a drawing of surface potentials present in the circuit of FIGURE 7;
lS FIGURE 9 is a clrawing of waveforms employed in the operatio~ of the circuit of FIGU~E 7; and FIGURE 10 is a section through an lnput circuit operated in accordance with another form of the present invention.
Tbe structure of the circuit of FIGURE 2 is very similar to that of FIGURE 1. However, the source S, rather than being operated at a fixed potential, is driven by a voltage V6 produced by source 20. The gate electrode Gl is operated at a fixed potential Vl. The gate electrode G2 is also operated at a fixed potential V2, where V2 is more negative than Vl. The gate electrode G3 is connected to .
a voltage source 22 which applies a negat~ V9 pulse V3 to this electrode.
The operation of the circuit may be understood by referring to FIGURE 3. The surface potentlal profiles shown ~g6~42 RCA 67,168 l represent the surface potentials existing at the source S and the various gates, the potential lines being aligned with the structures which produce these surface potentials.
At time t1 (surface potential profile a of FIGURE
3), the source diffusion S is at a relatively positive value such that it operates as a source of minority carriers (holes). Actually this relatively positive value may be several volts negative so that the PN junction formed by the source eiectrode may be slightly reverse biased. The gate electrode Gl is sufficiently negative that a conduction channel is present beneath this gate electrode. The gate electrode G2 is at a potential sufficiently negative that a potential well forms beneath this gate electrode. With these potentials, the charge carriers flow through the conduction channel and fill the eirst potential well to the level indicated. The depth of this first potential well can be considered as the surface potential difference ~W
between the source potential Vs and the initial surface - potential beneath electrode G2. The charge carriers cannot flow to the portion of the substrate surface beneath " electrode G4, as the third gate electrode G3 is at a relatively positive potential. This causes a potential barrier to è~ist between the potential well beneath electrode ` G2 and the potential well beneath electrode G4.
At time t2, the sourre potential Vs goes to a relatively negative value sufficiently so that the source S acts as a drain for charge carriers. Charge carriers now flow from the -first potential well and through the conduction channel beneath electrode Gl to the diffusion S, The effect 3 of changing the potential of the diffusion S is ~o reduce ~ 42 RCA 67,168 I the effeetive depth of the first potential well from dW
to ~W2.
In the introductory portion of this application, the noise problem is discussed. During the transfer of charge from the source diffusion to the first potential well (the well beneath gate G2) this same kind of noise is present here. This means that the charge signal initially present (time tl) may be no~sy, that is, its amplitude is not nccurately predictable. However, this is of no importance in the present system because this charge signal is not the one of interest and will not be the charge .signal which is propagated down the register.
At time t2, when the e~fectlve depth of the first potential well is reduced, the charge now in excess in the first well Elows through the conduction channel beneath G
bnck to the source S. ~f the potentials Vl and V2 are accurately maintained at a given level during this reverse flow of charge, the charge signal remaining in the first potential well will be relatively noise free. Although the reverse charge flow may be noisy, the surface charge beneath G2 is relaxing from a relatively high, somewhat uncertain value, to a lower value accurately defined by the difference between two surface potentials-Wl and W2. This reverse cbarge flow, however, does not stop abruptly but rather continues ~ue to thermal emission of charge from the first potential well, until a sufficiently large barrier forms between the surface potential beneath the electrode Gl and the ~uasi-Fermi level at the first potential well.
Because of the above thermal em~ssion the present process is not absolutely noise free and there is some thermal . .
~6~ RCA 67,168 1 noise present. This noise occurs because some ~a relatively small number) of the charge carriers stored in the first potential well are surficiently energetic to climb over the potential barrier Wl (see FIGURE 3b~ and escape from the . 5 potential well. These energetic carriers are illustrated schemati~lly at 24 and they result in a degree of uncertainty in the e~tent to which the first potential well is filled, designated by -the voltage EB, representing -the quasi-Fermi energy level for the charge in the first potential well.
However, this thermal noise ls a relatively small quantity ; which is proportional to the square root of both the cap-aci~ance and the absolute temperature, In numerical terms, .I the r.m.s. noise fluctuations in the input signal at room telllperature is expected to equal 400 ~ , where C is -the `~
e~fective capacitance of the first poltential well, in pico-f é~rads .
In one series of tests which were performed~ the total noise introduced (including thermal noise) in the storage of charge by the present method was found to be about one-third of that which is produced by the previous method in which the input signal had shot noise. The measurements of the previous method of introducing charge signal subject to partition noise found them to be more noisy than the previous method subject to shot noise.
The amount of charge signal introduced into the first potential well is proportional to the difference between the voltages Vl and V2. Accordingly, by making one of these quantities (V2~ the input signal and the other (Vl) a fixed voltage level, a charge slgnal can be introduced proportional to such signal.
, . , . ~ ; :
~ R~A 67,168 I As now well understood in this art, in some applications, in the interest of increased charge transfer efficiency, it is important always to have some residual charge present in the first potential well which is subse-quently propagated. Such a charge signal, sometimes known as "fat zero", may be introduced in the present system by proper choice in the difference in potential between V
and V2.
After introduction of the signal into the first potential well in the manner discussed above, it may be propagated by changing the value of the voltage V3 and applying the multiple phase voltages ~ 2~ and ~3. At time t3, the voltage V3 may be made relatively negative so as to form a relatively deeper potential well beneath electrode G3 than beneath electrode G2. At the same time, the first phase voltage ~1 is made e~en more negative than V3. The result of these actions is the propagation of charge signal from the potential well beneath electrode G2 to the potential well beneath G4 in the manner illustrated schematically at (c) in FIGURE 3. At time t4, V3 goes relatively positive again, forming a potential barrier.
- between the well be~th electrode G2 and the well beneath electrode G4. The process of establishing a new charge in the first potential well now can be started again and " 25 conc~rxently $he charge beneath electrode G4 can be shifted '~ to the right by the application of appropriate voltages 2 and ~3-Before leaving the subject of noise, one other aspect of this matter should be discussed. It is illustrated in FIGURE 3 at (c). At the time t3, there may be some :
. . ~.
RCA 67,168 1~96~:3142 1 relatively small number of charge carriers present beneath the gate electrode Gl. Some of these charge carriers that travel to the right and end up in the potential well beneath the electrode G4 result in additional noise fluctuations.
This type of noise is of the same kind as the partition noise already discussed. However, since the carriers of interest are only those present due to thermal noise, this partition noise is distinctly a second order effect in the present arrangement.
The circuit of FIG~RE 4 is a two-phase embodiment .
of the present invention. The structure is somewhat d:Lfferent than that of FIGURE 2 but the general principle of operation is the same. In the embodiment of FIGURE 4, the source electrode S is maintained at a fixed potential dif~`erence Vl from the first gate electrode 30 and acts l:Lke an extension of the source diffu~3ion. The second gate electrode 32 is ~aintained at a relat:lvely negative potential such that the sur-face potential benea-th this electrode is alwa~s more positive than that beneath electrode 30. In the example illustrated, this surface potential is -5 volts and it does not change. The thlrd gate electrode 34 is at some potential Vin proportional to the input signal. Since ; durin~any filling operation Vin remains at a relatively fixed value, the source of this voltage is illustrated as a 2S battery with an arrow through it indicating that the fixed value can be changed. The next pair of electrodes 36a, 36b can be considered the circuit for coupling the charge accumu-lated in the first potential well (the well beneath electrode 34~ to the remainder of the charge coupled register.
.
- ~ .
~9~ RCA 67,168 1 The operation of the circuit of FIGURE 4 is illustrated in FIGURES 5 and 6. At time tl, the source S
may be at, a potential of -3 volts and the gate electrode 30 nt a sufficiently negative potential to produce a -7 volt surface potential beneath gate 30. (The surface potential here and in the following figures is approximate and is for a substrate doping of 101 cm . Electrode 34 is at a potential such that the surface potential beneath this electrod~ is -~ volts. Accordingly, charge carriers initially flow through the conduction channel beneath electrode 30 and over the poten-tial barrier of -5 volts and into the first potential well. The effective depth of the first potential well is ~Wl which in this example is 5 volts.
At time t2, the source voltage has changed from -3 volts to -8 volts. At -3 volts, the source S acts as a source of charge carriers; however, at -8 volts the dif-fusion S ncts as a drain for chnrge carriers. The change in the voltage of the source diffusion from -3 volts to -8 volts `
effectively reduces the depth of the first potential ~ell from ~Wl = 5 volts to ~W~ = 3 volts. Some of the charge carriers fiowing out of the first potential well re~ain nccumulated in the -12 volts potential well which now exists beneath electrode 30. The remaining carriers, if any~ flow ` to the drain electrode. ;
Summarizing the steps above, at time tl the first potential well is relatively deep and fills to the extent of ~Wl; nt time t2 the effective depth of this well is reduced nnd n portion of the charge carriers formerly present is ~`
removed. As in the embodiment of FIGURE 1, the coming to equilibrium process is well defined depending only on the '`. . :
RCA 67,168 9~;~42 I accuracy with which the -8 volt and -5 volt surface potentials can be maintained and the charge remaining, ~W2, is accur-ately predictable.
At times t3 and t4, the charge present in the first potential well is first shifted into the well beneath electrode 36b and then is shifted to the first pair of phase electrodes of the charge coupled register. The process is believed to be self evident from the drawing and need not be discussed further.
In the embodiment of the invention illustrated in FIGURE 7, the source electrode S is maintained at a fixed potentinl Vs and the first electrode 30 is at a fi~ed potential difference Vl from the source electrode. Electrode 32 is driven by control voltage pulses V2(shown in FIGURE 9) and the input signal Vin may be applied between electrode 32 and electrode 3~. The remaining electrode pairs are con-ventionally operated by two-phase voltnges.
The operation of the FIGURE 7 circuit is illustrated in FIGURES 8 and 9. At time tl, the various potentials are sucb that the surface potential profile shown at (a) in `,!
EIGURE 8 exists. Charge carriers flow from the source electrode S through the conduction channel beneath electrode 30 and into the potential well beneath electrodes 32 and 34.
` The effective depth of this potential well is ~Wl = g volts.
At time t2, the voltage Va has gone from a rela-tively negative value of -21 volts to a relatively positive value of -75 volts, resulting in a change of the surface potential beneath electrode 32 from -10 to -Z volts and a change in the surface potential beneath electrode 34 from -15 volts to -5 volts. The result of this change in : ~ .
.. ~ .
.
: ::
RCA 67,168 ~g~42 potential of V2 is to change the effective depth of the first potential well from ~Wl = 9 volts to ~W2 = 3 volts. The charge formerly present in the first potential well flows in part into what now can be considered a potential well beneath electrode 30 and any excess charge flows into the source electrode S which now operates as a drain (note that while the source potential remains -6 volts, it is now more negative than the -2 volt surface potential beneath electrode 32). The charge ~W2 subsequently may be transferred in the manner indicated at (c) in FIGURE 8 and indicated also by the waveforms of FIGURE 9.
In some applications it may be desired that more time be available than shown by solid line in FIGURE 9 for the removal of a portion of the charge from the first potential well (from the well beneath electrode 34). In this case, the wave applied to the electrode pair 36a, 36b may be V3 rather than ~1' This wnve is shown in dashed line at the top of FIGURE 9. Note that this wave permits more time between the change of the voltage V2 from -21 volts 20 to -7 1/2 volts and the time at which the shifting of the charge beneath electrode 34 to beneath electrode 36~ begins.
Thus, mo.re time is available f~ settling, that is, for permitting the charge in the first potent~al well to come to equilibrium, before the shifting of charge begins.
For certain applications, such as charge-coupled devices image sensing lines or arrays, the low-noise electrically introduced background charge ("fat zero") already referred to can be introduced by a circuit such as shown in FIGURE 7 by maintaining Vin at a fixed potential level. Alternatively 3 a circuit such as shown in FIGURE 10 ; : .
~6~2 RCA 67,168 I may be employed. Here the operation is essentially identical with that of the FIGURE 7 circuit~ except that the potential hill created by electrode 32 relative to the potential well of electrode 34 is produced simply by the difference in relative spacings of these electrodes from the substrate.
In ~ther words, as the polysilicon electrode 34 is spaced substantially closer to the substrate than the electrode 32, even though both are at the same potential a relatively deeper well forms beneath electrode 34 than beneath electrode 32. The difference between these surface potentials beneath these electrodles defines the amplitude of the fat zero charge.
The operation of the FIGURE 10 embodiment is e~actl~y a~
clepicted in FIGURES 8 and 9.
Other alternatives for fat zero generation are to form n di~ference ln surface potentials beneath the electrode 32 and the electrode 3~ by means of charge in the oxide, by a ditference in substrate doping, or simply by the ditference in the work function of the two electrodes. This creates an asymmetrical potential well of the same type as just discussed.
, The Yarious forms of the invention shown in the present application are merely examples. It is to be under-stood that, for example, charge coupled circuits employing P type substrates rather than N type substrates may be operated in the same way as described, provided appropriate voltage levels are chosen. It is also to be understood that `:
~ 4~ RCA 67,168 1 different forms of electrode structures may be employed and also that the invention is applicable to four and higher phase systems.
The discussed concepts are also applicable for introducing low noise electrical input signals to the so-called buried channel charge-coupled devices in which case the charge flows not at the surface of the substrate but the potential minima for the charge carriers are formed at some small distance (on the order of 1.0 ~m) beneath the surface of the substrate. Also, while examples given here are for single registers, it is to be understood that these concepts apply to multiplicities of such registers as, for example, in the case of area image sensors.
`:
, .`~
: :
~ I ~
:., . ~ . . . . ... .
between the source potential Vs and the initial surface - potential beneath electrode G2. The charge carriers cannot flow to the portion of the substrate surface beneath " electrode G4, as the third gate electrode G3 is at a relatively positive potential. This causes a potential barrier to è~ist between the potential well beneath electrode ` G2 and the potential well beneath electrode G4.
At time t2, the sourre potential Vs goes to a relatively negative value sufficiently so that the source S acts as a drain for charge carriers. Charge carriers now flow from the -first potential well and through the conduction channel beneath electrode Gl to the diffusion S, The effect 3 of changing the potential of the diffusion S is ~o reduce ~ 42 RCA 67,168 I the effeetive depth of the first potential well from dW
to ~W2.
In the introductory portion of this application, the noise problem is discussed. During the transfer of charge from the source diffusion to the first potential well (the well beneath gate G2) this same kind of noise is present here. This means that the charge signal initially present (time tl) may be no~sy, that is, its amplitude is not nccurately predictable. However, this is of no importance in the present system because this charge signal is not the one of interest and will not be the charge .signal which is propagated down the register.
At time t2, when the e~fectlve depth of the first potential well is reduced, the charge now in excess in the first well Elows through the conduction channel beneath G
bnck to the source S. ~f the potentials Vl and V2 are accurately maintained at a given level during this reverse flow of charge, the charge signal remaining in the first potential well will be relatively noise free. Although the reverse charge flow may be noisy, the surface charge beneath G2 is relaxing from a relatively high, somewhat uncertain value, to a lower value accurately defined by the difference between two surface potentials-Wl and W2. This reverse cbarge flow, however, does not stop abruptly but rather continues ~ue to thermal emission of charge from the first potential well, until a sufficiently large barrier forms between the surface potential beneath the electrode Gl and the ~uasi-Fermi level at the first potential well.
Because of the above thermal em~ssion the present process is not absolutely noise free and there is some thermal . .
~6~ RCA 67,168 1 noise present. This noise occurs because some ~a relatively small number) of the charge carriers stored in the first potential well are surficiently energetic to climb over the potential barrier Wl (see FIGURE 3b~ and escape from the . 5 potential well. These energetic carriers are illustrated schemati~lly at 24 and they result in a degree of uncertainty in the e~tent to which the first potential well is filled, designated by -the voltage EB, representing -the quasi-Fermi energy level for the charge in the first potential well.
However, this thermal noise ls a relatively small quantity ; which is proportional to the square root of both the cap-aci~ance and the absolute temperature, In numerical terms, .I the r.m.s. noise fluctuations in the input signal at room telllperature is expected to equal 400 ~ , where C is -the `~
e~fective capacitance of the first poltential well, in pico-f é~rads .
In one series of tests which were performed~ the total noise introduced (including thermal noise) in the storage of charge by the present method was found to be about one-third of that which is produced by the previous method in which the input signal had shot noise. The measurements of the previous method of introducing charge signal subject to partition noise found them to be more noisy than the previous method subject to shot noise.
The amount of charge signal introduced into the first potential well is proportional to the difference between the voltages Vl and V2. Accordingly, by making one of these quantities (V2~ the input signal and the other (Vl) a fixed voltage level, a charge slgnal can be introduced proportional to such signal.
, . , . ~ ; :
~ R~A 67,168 I As now well understood in this art, in some applications, in the interest of increased charge transfer efficiency, it is important always to have some residual charge present in the first potential well which is subse-quently propagated. Such a charge signal, sometimes known as "fat zero", may be introduced in the present system by proper choice in the difference in potential between V
and V2.
After introduction of the signal into the first potential well in the manner discussed above, it may be propagated by changing the value of the voltage V3 and applying the multiple phase voltages ~ 2~ and ~3. At time t3, the voltage V3 may be made relatively negative so as to form a relatively deeper potential well beneath electrode G3 than beneath electrode G2. At the same time, the first phase voltage ~1 is made e~en more negative than V3. The result of these actions is the propagation of charge signal from the potential well beneath electrode G2 to the potential well beneath G4 in the manner illustrated schematically at (c) in FIGURE 3. At time t4, V3 goes relatively positive again, forming a potential barrier.
- between the well be~th electrode G2 and the well beneath electrode G4. The process of establishing a new charge in the first potential well now can be started again and " 25 conc~rxently $he charge beneath electrode G4 can be shifted '~ to the right by the application of appropriate voltages 2 and ~3-Before leaving the subject of noise, one other aspect of this matter should be discussed. It is illustrated in FIGURE 3 at (c). At the time t3, there may be some :
. . ~.
RCA 67,168 1~96~:3142 1 relatively small number of charge carriers present beneath the gate electrode Gl. Some of these charge carriers that travel to the right and end up in the potential well beneath the electrode G4 result in additional noise fluctuations.
This type of noise is of the same kind as the partition noise already discussed. However, since the carriers of interest are only those present due to thermal noise, this partition noise is distinctly a second order effect in the present arrangement.
The circuit of FIG~RE 4 is a two-phase embodiment .
of the present invention. The structure is somewhat d:Lfferent than that of FIGURE 2 but the general principle of operation is the same. In the embodiment of FIGURE 4, the source electrode S is maintained at a fixed potential dif~`erence Vl from the first gate electrode 30 and acts l:Lke an extension of the source diffu~3ion. The second gate electrode 32 is ~aintained at a relat:lvely negative potential such that the sur-face potential benea-th this electrode is alwa~s more positive than that beneath electrode 30. In the example illustrated, this surface potential is -5 volts and it does not change. The thlrd gate electrode 34 is at some potential Vin proportional to the input signal. Since ; durin~any filling operation Vin remains at a relatively fixed value, the source of this voltage is illustrated as a 2S battery with an arrow through it indicating that the fixed value can be changed. The next pair of electrodes 36a, 36b can be considered the circuit for coupling the charge accumu-lated in the first potential well (the well beneath electrode 34~ to the remainder of the charge coupled register.
.
- ~ .
~9~ RCA 67,168 1 The operation of the circuit of FIGURE 4 is illustrated in FIGURES 5 and 6. At time tl, the source S
may be at, a potential of -3 volts and the gate electrode 30 nt a sufficiently negative potential to produce a -7 volt surface potential beneath gate 30. (The surface potential here and in the following figures is approximate and is for a substrate doping of 101 cm . Electrode 34 is at a potential such that the surface potential beneath this electrod~ is -~ volts. Accordingly, charge carriers initially flow through the conduction channel beneath electrode 30 and over the poten-tial barrier of -5 volts and into the first potential well. The effective depth of the first potential well is ~Wl which in this example is 5 volts.
At time t2, the source voltage has changed from -3 volts to -8 volts. At -3 volts, the source S acts as a source of charge carriers; however, at -8 volts the dif-fusion S ncts as a drain for chnrge carriers. The change in the voltage of the source diffusion from -3 volts to -8 volts `
effectively reduces the depth of the first potential ~ell from ~Wl = 5 volts to ~W~ = 3 volts. Some of the charge carriers fiowing out of the first potential well re~ain nccumulated in the -12 volts potential well which now exists beneath electrode 30. The remaining carriers, if any~ flow ` to the drain electrode. ;
Summarizing the steps above, at time tl the first potential well is relatively deep and fills to the extent of ~Wl; nt time t2 the effective depth of this well is reduced nnd n portion of the charge carriers formerly present is ~`
removed. As in the embodiment of FIGURE 1, the coming to equilibrium process is well defined depending only on the '`. . :
RCA 67,168 9~;~42 I accuracy with which the -8 volt and -5 volt surface potentials can be maintained and the charge remaining, ~W2, is accur-ately predictable.
At times t3 and t4, the charge present in the first potential well is first shifted into the well beneath electrode 36b and then is shifted to the first pair of phase electrodes of the charge coupled register. The process is believed to be self evident from the drawing and need not be discussed further.
In the embodiment of the invention illustrated in FIGURE 7, the source electrode S is maintained at a fixed potentinl Vs and the first electrode 30 is at a fi~ed potential difference Vl from the source electrode. Electrode 32 is driven by control voltage pulses V2(shown in FIGURE 9) and the input signal Vin may be applied between electrode 32 and electrode 3~. The remaining electrode pairs are con-ventionally operated by two-phase voltnges.
The operation of the FIGURE 7 circuit is illustrated in FIGURES 8 and 9. At time tl, the various potentials are sucb that the surface potential profile shown at (a) in `,!
EIGURE 8 exists. Charge carriers flow from the source electrode S through the conduction channel beneath electrode 30 and into the potential well beneath electrodes 32 and 34.
` The effective depth of this potential well is ~Wl = g volts.
At time t2, the voltage Va has gone from a rela-tively negative value of -21 volts to a relatively positive value of -75 volts, resulting in a change of the surface potential beneath electrode 32 from -10 to -Z volts and a change in the surface potential beneath electrode 34 from -15 volts to -5 volts. The result of this change in : ~ .
.. ~ .
.
: ::
RCA 67,168 ~g~42 potential of V2 is to change the effective depth of the first potential well from ~Wl = 9 volts to ~W2 = 3 volts. The charge formerly present in the first potential well flows in part into what now can be considered a potential well beneath electrode 30 and any excess charge flows into the source electrode S which now operates as a drain (note that while the source potential remains -6 volts, it is now more negative than the -2 volt surface potential beneath electrode 32). The charge ~W2 subsequently may be transferred in the manner indicated at (c) in FIGURE 8 and indicated also by the waveforms of FIGURE 9.
In some applications it may be desired that more time be available than shown by solid line in FIGURE 9 for the removal of a portion of the charge from the first potential well (from the well beneath electrode 34). In this case, the wave applied to the electrode pair 36a, 36b may be V3 rather than ~1' This wnve is shown in dashed line at the top of FIGURE 9. Note that this wave permits more time between the change of the voltage V2 from -21 volts 20 to -7 1/2 volts and the time at which the shifting of the charge beneath electrode 34 to beneath electrode 36~ begins.
Thus, mo.re time is available f~ settling, that is, for permitting the charge in the first potent~al well to come to equilibrium, before the shifting of charge begins.
For certain applications, such as charge-coupled devices image sensing lines or arrays, the low-noise electrically introduced background charge ("fat zero") already referred to can be introduced by a circuit such as shown in FIGURE 7 by maintaining Vin at a fixed potential level. Alternatively 3 a circuit such as shown in FIGURE 10 ; : .
~6~2 RCA 67,168 I may be employed. Here the operation is essentially identical with that of the FIGURE 7 circuit~ except that the potential hill created by electrode 32 relative to the potential well of electrode 34 is produced simply by the difference in relative spacings of these electrodes from the substrate.
In ~ther words, as the polysilicon electrode 34 is spaced substantially closer to the substrate than the electrode 32, even though both are at the same potential a relatively deeper well forms beneath electrode 34 than beneath electrode 32. The difference between these surface potentials beneath these electrodles defines the amplitude of the fat zero charge.
The operation of the FIGURE 10 embodiment is e~actl~y a~
clepicted in FIGURES 8 and 9.
Other alternatives for fat zero generation are to form n di~ference ln surface potentials beneath the electrode 32 and the electrode 3~ by means of charge in the oxide, by a ditference in substrate doping, or simply by the ditference in the work function of the two electrodes. This creates an asymmetrical potential well of the same type as just discussed.
, The Yarious forms of the invention shown in the present application are merely examples. It is to be under-stood that, for example, charge coupled circuits employing P type substrates rather than N type substrates may be operated in the same way as described, provided appropriate voltage levels are chosen. It is also to be understood that `:
~ 4~ RCA 67,168 1 different forms of electrode structures may be employed and also that the invention is applicable to four and higher phase systems.
The discussed concepts are also applicable for introducing low noise electrical input signals to the so-called buried channel charge-coupled devices in which case the charge flows not at the surface of the substrate but the potential minima for the charge carriers are formed at some small distance (on the order of 1.0 ~m) beneath the surface of the substrate. Also, while examples given here are for single registers, it is to be understood that these concepts apply to multiplicities of such registers as, for example, in the case of area image sensors.
`:
, .`~
: :
~ I ~
:., . ~ . . . . ... .
Claims (5)
1. A charge-coupled circuit comprising, in combination:
a semiconductor substrate of one conductivity type;
a region in said substrate of different conductivity type;
a plurality of electrode means coupled to and insulated from said substrate for producing potentials at the substrate for the accumulation and propagation of charge signals originating at said region;
means for applying a potential to the first of said electrode means adjacent to said region for forming a conduction channel for charge carriers;
means for applying a potential to a second of said electrode means adjacent to said first electrode means for producing a potential well of a depth sufficient to accumulate charge carriers flowing through said conduction channel;
means for applying a potential to a third of said electrode means adjacent to the second of said electrode means for producing a first potential barrier at the substrate;
means for operating said region at a potential such that it produces charge carriers which flow through said conduction channel for an interval at least sufficient to fill said well to a given depth with carriers; and means for changing the difference in potential between said region and said second electrode means in a sense to permit said region to operate as a drain for charge carriers in excess in said potential well while relatively placing said first electrode means at a potential such that a RCA 67,168 potential barrier is present between said region and first well of a height lower than said first barrier and which permits a number of charge carriers to flow out of said well to said region sufficient to leave in said well charge at a desired level, said means for changing the difference in potential between said region and said second electrode means while relatively placing said first electrode means at a poten-tial such that a potential barrier is present comprising means for changing, in unison, the potentials of said first and second electrodes while maintaining the potential difference between them fixed, while maintaining said region at a fixed potential.
a semiconductor substrate of one conductivity type;
a region in said substrate of different conductivity type;
a plurality of electrode means coupled to and insulated from said substrate for producing potentials at the substrate for the accumulation and propagation of charge signals originating at said region;
means for applying a potential to the first of said electrode means adjacent to said region for forming a conduction channel for charge carriers;
means for applying a potential to a second of said electrode means adjacent to said first electrode means for producing a potential well of a depth sufficient to accumulate charge carriers flowing through said conduction channel;
means for applying a potential to a third of said electrode means adjacent to the second of said electrode means for producing a first potential barrier at the substrate;
means for operating said region at a potential such that it produces charge carriers which flow through said conduction channel for an interval at least sufficient to fill said well to a given depth with carriers; and means for changing the difference in potential between said region and said second electrode means in a sense to permit said region to operate as a drain for charge carriers in excess in said potential well while relatively placing said first electrode means at a potential such that a RCA 67,168 potential barrier is present between said region and first well of a height lower than said first barrier and which permits a number of charge carriers to flow out of said well to said region sufficient to leave in said well charge at a desired level, said means for changing the difference in potential between said region and said second electrode means while relatively placing said first electrode means at a poten-tial such that a potential barrier is present comprising means for changing, in unison, the potentials of said first and second electrodes while maintaining the potential difference between them fixed, while maintaining said region at a fixed potential.
2. A charge-coupled circuit comprising, in combination:
a semiconductor substrate;
a region in said substrate of different conductivity type than said substrate;
a plurality of electrode means coupled to and insulated from said substrate for producing potentials at the substrate for the accumulation and propagation of charge signals originating at said region, at least some of said electrode means driven by multiple phase voltages but the first and second of said electrode means, identified below, being disconnected from said multiple phase voltages;
means including said first of said electrode means close to said region and means for applying a potential to said first electrode means for forming a conduction channel for charge carriers in said substrate between said region and the portion of said substrate beneath said first electrode RCA 67,168 means;
means, including means for applying a signal potential between said second of said electrode means adja-cent to said first electrode means and said first electrode means, for producing a potential well in the substrate beneath said second electrode means of a depth sufficient to accumulate charge carriers flowing through said conduction channel;
means for applying a potential to a third of said electrode means adjacent to the second of said electrode means for producing a first potential barrier at the substrate;
means for operating said region at a potential such that it produces charge carriers which flow through said conduction channel for an interval at least sufficient to fill said well to a given depth with carriers;
and means for changing the difference in potential between said region and said second electrode means in a sense to permit said region to operate as a drain for charge carriers in excess in said potential well while said signal potential is present between said first electrode means and said second electrode means so that a potential barrier is present between said region and first well of a height lower than said first barrier and which permits a number of charge carriers to flow out of said well to said region sufficient to leave in said well charge at a level indicative of said signal potential.
a semiconductor substrate;
a region in said substrate of different conductivity type than said substrate;
a plurality of electrode means coupled to and insulated from said substrate for producing potentials at the substrate for the accumulation and propagation of charge signals originating at said region, at least some of said electrode means driven by multiple phase voltages but the first and second of said electrode means, identified below, being disconnected from said multiple phase voltages;
means including said first of said electrode means close to said region and means for applying a potential to said first electrode means for forming a conduction channel for charge carriers in said substrate between said region and the portion of said substrate beneath said first electrode RCA 67,168 means;
means, including means for applying a signal potential between said second of said electrode means adja-cent to said first electrode means and said first electrode means, for producing a potential well in the substrate beneath said second electrode means of a depth sufficient to accumulate charge carriers flowing through said conduction channel;
means for applying a potential to a third of said electrode means adjacent to the second of said electrode means for producing a first potential barrier at the substrate;
means for operating said region at a potential such that it produces charge carriers which flow through said conduction channel for an interval at least sufficient to fill said well to a given depth with carriers;
and means for changing the difference in potential between said region and said second electrode means in a sense to permit said region to operate as a drain for charge carriers in excess in said potential well while said signal potential is present between said first electrode means and said second electrode means so that a potential barrier is present between said region and first well of a height lower than said first barrier and which permits a number of charge carriers to flow out of said well to said region sufficient to leave in said well charge at a level indicative of said signal potential.
3. A charge-coupled circuit as set forth in claim 2 wherein said means for changing the difference in potential between said region and said second electrode means comprises means for changing the potential of said region while RCA 67,168 maintaining the potential of said first electrode means fixed.
4. A charge-coupled circuit as set forth in claim 2 wherein said means for changing the difference in potential between said region and said second electrode means while said first electrode means is at a potential such that a potential barrier is present comprises means for changing, in unison, the potentials of said first and second electrodes while maintaining the potential difference between them fixed and while maintaining said region at a fixed potential.
5. A charge-coupled circuit as set forth in claim 2, said first electrode means being laterally spaced from said region, and said means including said first electrode means for forming a conduction channel between said region and the portion of said substrate beneath said first electrode means further including an additional electrode coupled to the portion of the substrate means between said first electrode means and said region, said additional electrode maintained at a fixed potential offset from said region in a sense to form a conduction channel in a portion of the substrate beneath said electrode which extends from said region to the portion of the substrate beneath said first electrode means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36958073A | 1973-06-13 | 1973-06-13 | |
| US369,580 | 1973-06-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1096042A true CA1096042A (en) | 1981-02-17 |
Family
ID=23456040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA194,315A Expired CA1096042A (en) | 1973-06-13 | 1974-03-07 | Introducing signal to charge-coupled circuit |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS548428B2 (en) |
| CA (1) | CA1096042A (en) |
| DE (1) | DE2411606A1 (en) |
| FR (1) | FR2233713A1 (en) |
| GB (1) | GB1456255A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653865B2 (en) * | 1973-11-07 | 1981-12-22 | ||
| DE2543615A1 (en) * | 1975-09-30 | 1977-04-07 | Siemens Ag | REGENERATION STAGE FOR LOAD SHIFTING ARRANGEMENTS |
| US4191895A (en) * | 1976-07-26 | 1980-03-04 | Rca Corporation | Low noise CCD input circuit |
| US4191896A (en) * | 1976-07-26 | 1980-03-04 | Rca Corporation | Low noise CCD input circuit |
| NL7610351A (en) * | 1976-09-17 | 1978-03-21 | Philips Nv | LOAD TRANSFER DEVICE. |
| JPS5353278A (en) * | 1976-10-25 | 1978-05-15 | Fujitsu Ltd | Facet zero input system for charge transfer device |
| JPS5780773A (en) * | 1980-11-07 | 1982-05-20 | Nec Corp | Charge coupled device and driving method therefor |
| JPS5848464A (en) * | 1981-09-17 | 1983-03-22 | Nec Corp | Charge transfer device |
| DD231682A1 (en) * | 1984-12-20 | 1986-01-02 | Werk Fernsehelektronik Veb | INPUT CIRCUIT FOR LOAD-COUPLED COMPONENTS |
-
1974
- 1974-03-07 GB GB1023174A patent/GB1456255A/en not_active Expired
- 1974-03-07 CA CA194,315A patent/CA1096042A/en not_active Expired
- 1974-03-08 FR FR7407987A patent/FR2233713A1/fr not_active Withdrawn
- 1974-03-11 DE DE19742411606 patent/DE2411606A1/en active Pending
- 1974-03-12 JP JP2848074A patent/JPS548428B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2411606A1 (en) | 1975-01-09 |
| JPS5017940A (en) | 1975-02-25 |
| JPS548428B2 (en) | 1979-04-16 |
| FR2233713A1 (en) | 1975-01-10 |
| GB1456255A (en) | 1976-11-24 |
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