GB1579033A

GB1579033A - Linear ccd input circuit

Info

Publication number: GB1579033A
Application number: GB342/78A
Authority: GB
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1977-01-10
Filing date: 1978-01-05
Publication date: 1980-11-12
Also published as: DE2800893C2; DE2800893A1; DK149674C; PL203913A1; AU511885B2; FR2377127B1; ZA7810B; DK149674B; JPS56142670A; NL7800272A; DK8878A; AU3216678A; BE862760A; FR2377127A1; JPS5649460B2; FI72410B; NZ186177A; JPS5387675A; FI780012A; PL120630B1

Description

(54) LINEAR CCD INPUT CIRCUIT (71) We, RCA CORPORATION, a Corporation organized under the laws of the State of Delaware, United States of America, of 30 Rockefeller Plaza, City and State of New York, 10020, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention is directed to an improved charge coupled device (CCD) and particularly to the input circuit for such a device.

A charge coupled device, according to the prior art, comprises a substrate and electrodes insulated from the substrate. Multiple phase voltages applied to the electrodes form potential wells in the substrate for the storage and propagate charge signals along the length of the channel. The charge coupled device also includes a source electrode in the substrate.

Electrode means insulated from the substrate and located between the source electrode and the CCD channel are responsive to an input signal, for controlling the introduction of charge from the source electrode to the CCD channel.

According to the invention, the electrode means includes storage electrode means for forming an input potential well in the substrate in response to an applied voltage which input potential well is substantially larger than the capacity of the potential wells in the CCD channel. The input potential well has a signal voltage versus number-of-chargecarriers-introduced transfer function, which is relatively non-linear at lower input signal levels and relatively linear at higher input signal levels. In order to overcome the problem presented by this nonlinear transfer function, there is provided means responsive to the input signal and to a control voltage manifestation for introducing into the input potential well a charge which includes a bias component at a level which corresponds to the non-linear region of said transfer characteristic and further includes a signal component. Also provided is means for removing from said input potential well beneath the storage electrode the signal component of the charge stored therein and for propagating that signal component to the CCD channel, while retaining the input potential well beneath the storage electrode the bias component of the charge.

In the drawings: Figure 1 is a graph of input signal voltageversus-charge carriers produced, in a conventionally operated buried channel CCD input stage; Figure 2 is a plan view of a CCD input circuit embodying the present invention; Figure 3 is a section taken along line 3-3 of Figure 2; Figure 4 is a drawing of substrate potential profiles to help explain the operation of the circuit of Figures 2 and 3; Figure 5 is a drawing of waveform timing employed in the operation of the circuit of Figures 2 and 3; and Figures 6a and 6b are graphs to help explain the operation of the circuits of Figures 2 and 3.

U.S. Patent No. 3,986,198 issued October 12, 1976 to Walter F. Kosonocky describes relatively noise-free circuits for introducing a charge signal into a CCD register. The technique employed has become known as the "fill and spill" mode of operation.

Charge signal is introduced from a source electrode to a first potential well, this being the fill portion of the cycle. Then, the potential well is partially emptied, for example by operating the source electrode as a drain.

During the emptying process, an input signal potential is maintained between the electrode under which the potential well is formed and a second electrode between that electrode and the source electrode. The charge which remains in the first potential well is a function of the amplitude of this input signal and is relatively noise free.

It has been found that when the CCD is a buried channel CCD, the operation described above, while relatively noise free, results in relatively non-linear translation of the input signal to charge (as compared to the signal translation which occurs in a surface channel CCD). The transfer characteris tic of signal voltage versus number of charge carriers produced for a typical buried N-channel CCD, is shown in Figure 1. The flat region 11 at the top represents the charge capacity of the input potential well and it may be slightly greater than that of each transfer potential well along the major part of the CCD channel. The capacity of such a transfer potential well is represented by dashed line 13.

The curve includes a relatively non-linear region at relatively low signal levels (between Vzvolts and Vx) and a relatively linear region at relatively high signal levels (between Vx and Vy). A change in signal level AVINi at a relatively low input signal level is translated non-linearly to a charge signal in the input potential well; a change in input signal A VIN2 at a relatively high input signal level is translated linearly to a charge signal in the input potential well. The non-linear region results, for example, from the characteristic of a buried channel device that the capacitance of the buried channel varies more as a function of charge level at lower values of charge than at higher values of charge. There are also more complex effects which influence the degree of non-linearity.

In certain applications as, for example, in CCD delay lines employed to delay analog signals such as the video signals of television, operation as discussed above is, of course, highly disadvantageous. It is desirable that the CCD delay line introduce as little distor fion as possible to the analog signal and to do this, the input circuit to the CCD should operate in linear fashion.

It is also important that a CCD delay line as described above not occupy excessive area on the semiconductor substrate. The CCD is designed to have a channel width and electrode areas such that the potential wells which are formed in response to the multiple phase voltages can store only as much charge as can be produced by the greatest amplitude input signal expected (assuming some practical value such as 10-12 volts or so of multiple phase voltage). If the CCD electrode areas are made larger, it means that each CCD delay line is larger and this, in turn, means that fewer such CCD delay lines can be obtained from a single wafer (in practice, many delay lines are fabricated at the same time on the same wafer and are then cleaved or separated in some other way from one another). This is wasteful and adds to the expense of each line. In addition, larger area delay lines exhibit greater capacitance and this makes operating them at high frequencies (high frequency multiple phase voltages) more difficult and requires greater power dissipation in the CCD driver circuits.

Figures 2 and 3 illustrate a circuit embodying the invention which solves the problems above. The CCD includes a P-type silicon substrate 10 and a source electrode S at the substrate surface. This source electrode may comprise an N-type diffusion in the P-type substrate. The layer B comprises a thin layer of N-type silicon at the substrate surface and forming a PN junction 12 with the substrate.

Layer B, as is well understood in the art, is less highly doped than the source diffusion S.

The CCD input electrodes comprise three gate electrodes G1, G2 and G3, in that order, followed by multiple phase electrodes 14, 16, 18, 20 and so on. By way of illustration, these electrodes may all be formed of polysilicon and may be the overlapped, two-layer type.

Of course other materials and other forms of construction are possible and within the scope of the present invention. The CCD channel, which may be defined by channel stop diffusions (not shown), is relatively wide beneath the input electrodes G1, G2 and G3 and tapers down to a narrower width for the major part of the CCD as illustrated by dashed lines. This major part of the CCD (not shown) may include several hundred CCD stages (over 500 in one practical design, with four electrodes, per stage). In the embodiment illustrated, the wider portion of the CCD channel may have a width double that of the major portion of the CCD channel as indicated by the widths 2w and w, respectively, in Figure 2.

The operation of the CCD is depicted in Figures 4 and 5. It is assumed for purposes of illustration that at time to, no charge is present in the potential well 26 beneath electrode G2 as indicated at a of Figure 4. At this time, 1 is low so that there is a potential barrier 20 beneath the first 01 electrode 14 and a shallow potential well 22 beneath the electrode 16. The shallow well occurs because electrode 16 is maintained at a direct voltage offset which is relatively positive compared to the voltage at electrode 14. This is indicated schematically by the battery 15. V8 is at a relatively low level at this time so there is a potential barrier 24 beneath electrode G3.

V2 continuously is maintained at a relatively high dc level so that a poetntial well 26 is present beneath storage electrode G2. This well may be considered the "input" potential well. V1 also is a dc level but it is less positive than V2. This voltage and the signal voltage VIN are applied to electrode G1. Accordingly, there is continuously present beneath electrode G1 a potential barrier whose height is a function of the dc level V1 plus the signal level VIN. The voltage Vs is relatively positive at time to so that diffusion S acts as a drain for charge carriers.

At time t1, the voltage Vs is relatively negative so that the diffusion S operates as a source of charge carriers. These charge carriers (electrons) now fill the potential well 26 to the level 30.

At time t2, the voltage Vs is at its more positive value, causing the diffusion S to operate as a drain. Now some of the charge present in well 26 spills back over the barrier 28 and into region S. The charge remaining in potential well 26 includes one component proportional to signal and another proportional to the difference in dc levels between V1 and V2. In the drawing, the charge in well 26 is cross-hatched in two different ways.

One part 32 of this charge will continuously remain in this well and it is legended "bias." The remainder 34 of the charge, legended "signal" will be "skimmed" from the well and propagated down the CCD register as will be explained shortly.

At time t3, V8 is relatively positive so that the height of barrier 24 is substantially lower than it was at time t2. The voltage V2 applied to the storage electrode G2 remains the same, as already mentioned. At time t3 also, the Phase 1 voltage l is high so that potential wells 36 and 38 are present beneath the l electrodes 14 and 16, respectively. As electrode 16 is biased more positively than electrode 14, the well 38 beneath electrode 16 is deeper than the well 36 beneath electrode 14.

(While for purposes of the present discussion a means 15 providing a voltage offset between two electrodes is shown for producing an asymmetrical potential well, alternative structures are possible. One is to employ a single electrode in place of the two such as 14, 16 and to employ a suitable ion implant under one of them.) The l voltage is of substantially greater amplitude than the V8 voltage at time t3 so that well potential 20 is higher than (appears as a potential well relative to) well potential 24. In response to these conditions, a portion of the charge in potential well 26 is skimmed from this well and propagated to well 38. The remainder of the charge, the bias charge 32, continues to remain in potential well 26. The portion 34 of the charge formerly in well 26 and now in well 38 subsequently is propagated down the CCD register by the two phase voltages 0,, 2 in conventional fashion.

The significance of the operation in the way described may be better appreciated by referring to Figure 6a. This graph is drawn to smaller scale than Figure 1 (assuming dashed line 13 represents the same charge level in both figures, note that this dashed line ii roughly twice as far from the zero charge level than the same line in Figure 6a) but the same reference numerals are employed to describe similar parts of the graph. The potential well 26 (Fig. 4) continuously retains a bias charge (32 of Figure 4) which is represented by the dashed line 15 of Figure 6. This dashed line defines the start of the relatively linear region of the transfer curve. Any charge added to this potential well in response to an input signal VIN results in substantially linear translation of this input signal to charge (34 of Figure 4) because the operation is in the linear region of the characteristic.

Moreover, the structure is such that full dynamic range is obtained. In other words, because the input potential well (the well beneath electrode G2) is in a region where the channel is wide, its capacity is relatively large-approximately double that of the CCD transfer wells in the major part of the CCD (the input well beneath electrode G2 has approximately double the capacity of a well beneath an electrode such as 42 of Figures 2 and 3). This means that even though the potential well 26 beneath storage electrode G2 is available to accept signal charge up to only a fraction of its capacity (assume that when the input signal is at its maximum value, it occupies only one half the well, the bias charge occupying the remainder of the well), the charge signal skimmed from this potential well 26 still can fill the well beneath electrode 42 to substantially its entire capacity, at maximum input signal level. Thus, the CCD described operates linearly over substantially the full capacity of the transfer potential wells in the body of the CCD and therefore has wider useful dynamic range.

The transfer function of a typical transfer potential well such as one beneath electrode 42 of Figs. 2 and 3 as related to the input signal VIN applied to electrode G, is illustrated in Figure 6b. The full transfer well capacity is illustrated at 13. Note that the operation is quite linear over almost the entire characteristic. (It is found, in practice, that at extremely low input signal VIN levels, some minor non-linearity is introduced as shown at 17, but the reason is not yet fully understood.) The substantially linear operation described above is achieved without requiring excessive substrate area. In one practical design, the maior part of the CCD comprises over 500 stages (over 2,000 electrodes) and the channel width, electrode areas and substrate areas of all except the first of these stages remain unchanged. The electrodes 14, 16, 18, 20 of this first stage are increased in area, one additional gate electrode G3 is employed and the source electrode and first two gate electrodes are increased in area.

The total increase in size required of the CCD is not significant-only a fraction of a percent.

While for purposes of illustration two phase operation is assumed, it is of course to be appreciated that the invention is equally applicable to three, four or higher phase operation. It is also to be understood that while the CCD illustrated employs a P-type substrate, it is equally applicable to N-type substrate devices employing P-type surface layers and a P-type source region. Of course, appropriate changes in operating voltages are required. Further, while typical waveforms are illustrated, modifications are possible.

For example, the voltage V8 is shown to have the same shape as the wave 0,. How ever, proper operation can still be obtained with V8 of different shape than V1. V8 should be low at the time Vs is low, however, V8 can go high before 0, goes high.

While not illustrated, the system disclosed can employ the technique illustrated in either of two copending U.K. patent appli cations identified below for insuring that the source electrode operates at proper potentials during the fill and spill operation. These are our applications nos. 30630/77 (Serial No.

1,579,031) and 30631/77 (Serial No.

1,579,032).

WHAT WE CLAIM IS:- 1. A method of operating a CCD of the type which has an input potential well transfer function of number of charge carriers produced versus input signal voltage which is relatively non-linear in a first input signal range between first and second signal levels, V1 and V2, respectively and which is relatively linear in a second input signal range between said second level V2 and a third signal level V3, where the first, second and third levels are of successively higher values, the steps of: placing a bias charge in said input poten tial well at a level corresponding to the num ber of charge carriers which would be pro duced in response to an input signal at sub stantially said second signal level V2; adding to said bias charge in said input potential well, a number of charge carriers proportional to an input signal whose ampli tude is in the range of zero to (V8-V2); skimming from said potential well only that portion of the charge therein which exceeds said bias charge signal; and transmitting said skimmed charge portion along the length of said CCD by propagating the same in potential wells of substantially smaller capacity than said input potential well but still of sufficient capacity to store a charge corresponding to the maximum input signal level V8-V2.

2. The method of claim 1, wherein the step of adding to said bias charge a number of charge carriers proportional to said input signal comprises first adding a greater num ber of such charge carriers to said input potential well and then, in response to said - input signal, removing from said input potential well as sufficient number of charge carriers to leave stored in said well a number corresponding to said bias charge plus the number proportional to said input signal.

3. A charge coupled device which in cludes: a CCD channel comprising a substrate and electrodes insulated from the substrate to which multiple phase voltages may be applied for forming potential wells in the substrate for the storage and propagation of charge signals along the length of said channel; a source electrode in the substrate; electrode means insulated from the substrate and located between the source electrode and the CCD channel, said electrode means being responsive to an input signal for controlling the introduction of charge from said source electrode to said CCD channel, and including storage electrode means for forming an input potential well in said substrate in response to an applied voltage, which input potential well is substantially larger than the capacity of the potential wells in said CCD channel and has a signal voltage versus number of charge carriers introduced transfer function which is relatively non-linear at lower input signal levels and relatively linear at higher input signal levels; means responsive to said input signal and a control voltage manifestation for introducing into said potential well a charge which includes a bias component at a level corresponding to the non-linear region of said transfer characteristic and a signal component; and means for removing from said input potential well beneath said storage electrode the signal component of the charge stored therein and propagating the same to said CCD channel while retaining the bias component of said charge in said potential well beneath said storage electrode.

4. The charge coupled device set forth in claim 3 wherein said charge coupled device comprises a buried channel charge coupled device.

5. The charge coupled device set forth in claim 3 or 4 wherein said means responsive to said input signal and said control voltage manifestation comprises: a control electrode to which said signal is applied, said control electrode being insulated from the substrate and located between said storage electrode and said source electrode; and means for applying said control voltage manifestation between said source electrode and said control electrode at one value during one interval of time for filling said potential well beneath said storage electrode with charge and at another value during a following interval of time for removing a portion of said charge, thereby to leave in said potential well said charge which includes said signal component and said bias component.

6. The charge coupled device as set forth in claim 3 or 4 wherein said electrode means includes storage electrode means for making the depth of said input potential well at least double the size of the potential wells in said CCD channel.

7. A charge coupled device input circuit comprising:

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. For example, the voltage V8 is shown to have the same shape as the wave 0,. How ever, proper operation can still be obtained with V8 of different shape than V1. V8 should be low at the time Vs is low, however, V8 can go high before 0, goes high. While not illustrated, the system disclosed can employ the technique illustrated in either of two copending U.K. patent appli cations identified below for insuring that the source electrode operates at proper potentials during the fill and spill operation. These are our applications nos. 30630/77 (Serial No. 1,579,031) and 30631/77 (Serial No. 1,579,032). WHAT WE CLAIM IS:-

1. A method of operating a CCD of the type which has an input potential well transfer function of number of charge carriers produced versus input signal voltage which is relatively non-linear in a first input signal range between first and second signal levels, V1 and V2, respectively and which is relatively linear in a second input signal range between said second level V2 and a third signal level V3, where the first, second and third levels are of successively higher values, the steps of: placing a bias charge in said input poten tial well at a level corresponding to the num ber of charge carriers which would be pro duced in response to an input signal at sub stantially said second signal level V2; adding to said bias charge in said input potential well, a number of charge carriers proportional to an input signal whose ampli tude is in the range of zero to (V8-V2); skimming from said potential well only that portion of the charge therein which exceeds said bias charge signal; and transmitting said skimmed charge portion along the length of said CCD by propagating the same in potential wells of substantially smaller capacity than said input potential well but still of sufficient capacity to store a charge corresponding to the maximum input signal level V8-V2.

7. A charge coupled device input circuit comprising:

a semiconductor substrate; a source electrode in said substrate; a CCD buried channel ("CCD CHAN NEL") in said substrate comprising a first region adjacent to said source electrode, a substantially narrower third region comprising the major portion of the CCD, and a second tapering region which joins the input and third regions; first, second and third electrodes over said first region and insulated from said substrate, said second electrode comprising a storage electrode, said first electrode being located between said storage electrode and said source electrode, and said third electrode being located between said second electrode and said second region of said CCD channel; means for applying a voltage to said second electrode for creating a potential well in said substrate; means for applying an input signal to said first electrode; means for applying a difference in potential between said source and first electrodes of a value to fill said potential well with charge and then of a value to spill some of said charge back into said source electrode, to leave in said well a charge which includes a signal component and a bias component, said bias component occupying a substantial portion of said well; means for maintaining said third electrode at a potential to form a barrier in said substrate during at least the period said potential well is being filled; electrodes over said third region responsive to multiple phase voltages for creating potential wells in the substrate of substantially smaller capacity than the potential well beneath said second electrode but of sufficient capacity to store and propagate said signal component; means for changing the potential applied to said third electrode to a value such that that portion of the charge in said potential well beneath said second electrode, which portion exceeds said bias level, can flow over the reduced potential barrier beneath said third electrode; and means in said second region of said CCD channel for transferring said charge which flows over said reduced potential barrier to said third region of said channel.

8. A charge coupled device substantially as hereinbefore described with reference to the accompanying drawings.