FI72410C - LADDNINGSKOPPLAD ANORDNING OCH FOERFARANDE FOER DESS DRIVANDE. - Google Patents

Description

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c (45) Patent isyc-i-nctty P-'H -'- 'nt. · «] '-' ·· fc ii 0Π 10 O7 (51) Kv.lk.4 / lnt.CI. * H 01 L 29/78 FINLAND —FINLAND (21) Patent application - Patentansökning 780012 (22) Application date - Ansökningsdag 03.01 .78 (EN) (23) Date of commencement— Giltighetsdag 03.01 .78 (41) Has become public - Blivit offentlig 1 j .07.78

National Board of Patents and Registration Date of publication and publication. _

Patent and registration authorities '' Ansökan utlagd och uti.skriften publicerad 3O.OI.87 (86) Kv. application - Int. trap (32) (33) (31) Claim claimed privilege - Begärd priority 10.01 77 USA (US) 75818 ** (71) RCA Corporation, 30 Rockefeller Plaza, New York, New York, USA (US) (72) James Edward Carnes , North Brunswick, New Jersey,

Peter Alan Levine, Trenton, New Jersey,

Donald Jon Sauer, Plainsboro, New Jersey, USA (US) (7 * 0 Oy Koi ster Ab (5 **) Reservation i i rtorek i s ter i and method for its use -

The present invention relates to a method for using a charge transfer register (CCD) as described in the preamble of claim 1, and to a charge transfer register for such a method.

According to the state of the art, the charge-connected device has a base and electrodes isolated therefrom. The multi-phase voltages applied to the electrodes cause potential pits in the substrate to store and transmit charge signals along the channel. The base of the charge-connected device also has an emitter electrode. Electrode devices isolated from the substrate and located between the emitter electrode and the CCD channel respond to the input signal and direct the charge of the emitter electrode to the CCD channel.

According to the invention, the electrode devices have a deposit electrode device for forming a potential well on the substrate controlled by the input voltage, which is substantially larger than the capacity of the potential wells of the CCD channel. The input potential well has a transfer function whose variables are the signal voltage and the number of charge carriers and which is relatively non-linear at low input signal levels and relatively linear at higher input signal levels. This problem caused by the nonlinear transfer function is characterized by the method according to the invention as described in the characterizing part of claim 1. The charge transfer register according to the invention is in turn characterized in that the channel width in the part controlled by the input electrodes is larger than the width of the extension channel, whereby the charge capacity of the input potential well is larger than the charge capacities of the corresponding potential wells of said extension channel.

The invention will now be described in more detail with reference to the examples according to the accompanying drawings, in which Fig. 1 shows a curve in which the number of charge carriers is expressed as a function of input signal voltage at a conventional burial channel CCD input stage, Fig. 2 shows a CCD input circuit according to the present invention. -3 section, Fig. 4 shows substrate potential profiles that facilitate understanding of the circuit operation of Figs. 2 and 3, Fig. 5 shows the timing of the waveforms occurring when the circuit of Figs. 2 and 3 operates, and Figs. 6 and 6b show curves facilitating understanding of the circuit operation of Figs.

U.S. Patent No. 3,986,198 (October 12, 1976 to Walter F. Kosonocky) discloses relatively noise-free circuits for introducing a charge into a CCD register. This technique has become known as "filling and peeling". The charge signal is applied from the emitter electrode to the first potential well during the cycle filling time. The well is then partially emptied, for example by using an emitter electrode as a collector. During discharge, the input signal potential is maintained between the electrode under which the potential well is formed and the second electrode located between this electrode and the emitter electrode. The charge remaining in the first potential well is a function of the amplitude of this input signal and is relatively noiseless.

It has been found that when the CCD device is a buried channel CCD, the operation described above, although relatively noisy, causes the relatively nonlinear input signal to change to a charge (compared to the signal conversion of a surface channel CCD device). Fig. 372410 sa 1 shows the transfer function of a buried N-channel CCD device, in which the variables are the signal voltage and the number of charge carriers formed. The straight area 11 above corresponds to the charge capacity of the input potential well, and may be slightly larger than the charge capacity of each transmission potential well along the main part of the CCD channel. The capacity of such a transfer potential well is indicated by dashed line 13.

The curve is relatively non-linear at relatively low signal levels (between V -V) and relatively linear at relatively low

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at high signal levels (between νχ and ν ^). A change in signal level at a relatively low signal level is transmitted from a nonlinear input potential well to a charge signal. The nonlinear range is due, for example, to the characteristic curve of the buried channel device, because the capacitance of the buried channel changes more as a function of the charge level at low charge levels than at higher charge levels.

More complex phenomena also affect the amount of nonlinearity.

In certain applications, e.g. in the delay lines of the video signals of a television receiver, this operation as described above is, of course, very disadvantageous. It is desirable that the CCD delay line cause as little distortion to the analog signal as possible, and therefore the input circuit of the CCD must operate linearly.

It is also important that the CCD delay line described above does not take up too much space on the semiconductor substrate. The CCD is designed for a channel width and electrode area such that potential wells caused by multi-phase voltages can store as much charge as the input signal with the largest expected amplitude can produce (for a multi-phase voltage, some practical value is assumed, e.g. 10-12 V). If the CCD electrode areas are made larger, each CCD delay line also becomes larger, and this in turn means that fewer delay lines are provided for each individual piece (in practice, many delay lines are made on the same piece at the same time, which are then separated in some way). This is a waste and increases the cost of each line. In addition, larger delay lines have higher capacitance, which makes operation at high frequencies (high-frequency multi-phase voltages) even more difficult and requires higher power consumption in CCD control circuits.

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Figures 2 and 3 show a circuit according to the present invention with which the above-mentioned problem can be solved. The CCD has a P-type silicon substrate 10 and an emitter electrode S on its surface. This electrode can be an N-type dopant. Layer B has a thin layer of N-type silicon on the surface of the substrate so that a PN bond 12 is formed with the substrate. As is well known in the art, layer B is less doped than emitter mixture S. CCD input electrodes have three gate electrodes, G2 and G1, respectively. , followed by multiphase electrodes 14,16,18,20, etc. These electrodes can all be e.g. polysilicon and a superimposed bilayer type. Other materials and structures are, of course, possible and are within the scope of this invention. The CCD channel, which can be determined by channel stop mixtures (not shown), is relatively wide under the input electrodes G 1, G 1 and G 1 and tapers to a smaller width from the main part of the CCD channel, as shown by the dashed lines. This main part of the CCD channel (not shown) may contain several hundred CCD degrees (one practical structure has 500 degrees, each with four electrodes). In the embodiment shown here, the width of the wider part of the CCD channel may be twice the width of the main part of the channel, as shown by the widths 2w and w in Fig. 2.

The operation of the CCD channel is shown in Figures 4 and 5. By way of example, it is assumed that at time t there is no charge in the potential well 26 below the electrode G2 (Figure 4). At present, 01 is so small that there is a potential meter 20 below the first 0 ^ electrode 14 and a low potential well 22 under the electrode 16. The low well is due to the maintenance of a DC voltage difference in the electrode 16 which is relatively positive compared to the electrode 14. voltage. This is shown schematically by the battery 15. is at a relatively low level at present, so there is a potential wall 24 under the electrode G1. V2 is kept at a relatively high DC voltage level so that there is a potential well 26 under the deposit electrode G2. This can be considered as an "input potential well". V1 is also at the DC voltage level, but it is less positive than V2. This voltage as well as the signal voltage VIN are applied to the electrode G1. As a result, there is a continuous potential wall below the electrode G-, the height of which is a function of the sum of the DC voltage level and the signal level VIN. The voltage Vg is relatively positive at time t, so the diffusion S acts as a collector of charge carriers.

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At time t1, the voltage Vg is relatively negative, so the diffusion S acts as the emitter of the charge carriers. These charge carriers (electrons) now fill the potential well 26 to level 30.

At time t £ the voltage Vg is more positive, and the diffusion S acts as a collector. Now, part of the charge in the well 26 is discharged back over the wall 28 into the region S. The charge remaining in the well 26 contains one component proportional to the signal and another component proportional to the difference between the V 1 and the DC voltage levels. In the figure, the charge of the well 26 is slashed in two different ways. Part 32 of this charge remains continuously in the pit and is marked as a pre-charge. The rest of the charge 34, i.e. the signal, is "peeled" from the well and transferred to the CCD register as described below.

At time t1 V1 is relatively positive, so the wall 24 is substantially lower than at time t2 * The voltage V2 applied to the deposit electrode remains the same as already mentioned. At time t1, the voltage of phase 1 is high, so there is a potential well 36 under the electrode 14 and a well 38 under the electrode 16. Since the electrode 16 is pre-charged more positive than the electrode 14, the well 16 below it is deeper than the well 36. (Although between the electrodes the voltage separation device 15 has been described for this representation as forming an asymmetric potential well, other structures are possible (one possibility is to use one electrode instead of two and a suitable ion mixture below it). The voltage 0 ^ is substantially larger in amplitude than at present, so that the well potential 20 is higher than the well potential 24 (i.e., 20 appears as a well as seen from well 24). Under these conditions, the charge portion of well 26 is erased from the well and transferred to well 38. The remaining charge portion, pre-charge 32, remains in well 26. The charge portion 34 originally in well 26 and now in well 38 is then transferred along the CCD register to phase voltages 0 and effect in the usual way.

The significance of this function may be easier to understand with reference to Figure 6. In it, the curve is drawn on a smaller scale than in Figure 1 (assuming that the dashed line 13 shows the same charge level in both figures, this dashed line is approximately twice as far from the zero charge level as the same line in Figure 6a), but the reference numbers are kept unchanged. The potential well 26 continuously retains the pre-charge 6,72410 (Fig. 4) (32 in Fig. 4) shown by the dashed line 15 in Fig. 6. This dashed line determines the starting point of the relatively linear portion of the transfer curve. Any charge added to this potential well (due to the input signal) causes the input signal to change (34 in Figure 4) to a charge substantially linearly, since the operation takes place on the linear part of the characteristic curve. In addition, the structure is such that the full dynamic range is maintained. That is, since the input potential well (the well below the electrode G2) is in the wide part of the channel, its capacity is relatively large - about twice the capacity of the transfer wells of the main channel of the CCD channel (about twice the capacity of the well below the electrode G2 compared to e.g. 2 and 3, to the capacity of the well below).

This means that although the well 26 below the deposit electrode G2 can only receive a signal charge at part of its capacity (assuming the input signal is at its maximum, filling only half of the well when the pre-charge fills the rest), the charge signal peeled from the well 26 can still fill the well below the electrode 42 substantially full at the maximum input signal. The CCD described herein thus operates linearly at substantially the full capacity of the transfer wells in the CCD body, and thus has an even wider usable dynamic range.

The transfer function of a typical transfer potential well (e.g., below the electrode 42 of Figures 2 and 3) is shown in Figure 6b with respect to the input signal applied to the electrode G. The full capacity of the transfer well is 13. It should be noted that the operation is very linear over almost the entire characteristic curve. In practice, it is observed that at very low levels of the input signal there is a small nonlinearity - in Figure 17 - but the reason for this is not yet fully understood).

The substantially linear operation described above is achieved without the use of excessive substrate areas. In one practical application, the main part of the CCD has more than 500 degrees (more than 2000 electrodes), and with the exception of the first of all these degrees, the channel width, electrode area, and substrate area can remain unchanged. The first stage electrodes 14, 16, 18 and 20 are larger in area, have one additional electrode G and an emitter electrode, and the first two helix electrodes have a larger surface area. The total size increase needed by the CCD is insignificant - only a fraction of a percent.

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Although a two-stage operation has been proposed by way of example, it is, of course, clear that the invention may equally well be applied to a four-stage or multi-stage operation. It is also to be understood that although the CCD disclosed herein has a P-type substrate, it is equally applicable to N-type substrates using P-type surface layers and a P-type emitter region. In this case, of course, the necessary changes must be made to the operating voltages. In addition, although nitrogen waveforms are shown here, their transformations are possible. For example, the voltage is shown in the same form as 0 ^. However, proper operation is achieved by making it different from V ^ j. V ^ should be small when Vgi is small, but can still rise before 0 ^ rises.

Although not shown herein, the technique of the two co-pending patent applications detailed below can be used in this system to ensure that the emitter electrode operates at the correct potentials during the filling and emptying operation. These patent applications are U.S. Patent Applications No. 708,351 (filed June 26, 1976 to Peter A. Levine and Donald J. Sauer) entitled "Low Noise CCD Tux Circuit" and No. 708,397 (filed June 26, 1976 to Donald J. .Sauer and Peter A. Levine) called "Low Noise CCD Input Circuit". Both of these applications have been assigned to the same assignee as this patent application.

Claims (5)

A method of driving such a semiconductor element designed charge coupled device (CCD) whose transfer function of an input potential pit for a plurality of charge carriers generated in response to input signal voltage is relatively non-linear in a first input signal range between a first signal level 2 and a second signal level 2. linear in a second input signal range between said second level V2 and a third signal level, wherein the first, second and third levels have successively higher values and wherein a number of charge carriers, the number of which corresponds to the input signal, are fed into the potential pit and the charge contained in the the potential pit is pulled out and transmitted into the potential pits by the CCD semiconductor element continuity channel along the length of the elements, characterized by the following steps: a) placing a preload in the potential pit at a level corresponding to the number of charge carriers to be generated in response to an input signal which is substantially equal to said second screen bn level V2, b) adding a plurality of charge carriers to the charge in the potential pit, which charge carrier corresponds to an input signal whose amplitude is in the range 0.. . (D) - (c) displacement from the potential pit of the charge portion exceeding the precharge signal, and d) transmitting said offset charge along the length of the CCD semiconductor element by moving the charge into potential pits, the capacity of which is substantially smaller than the input potential pit. but whose capacity is still sufficient for storing a charge corresponding to the maximum input signal level V3 “V2 * 2. A method according to claim 1, characterized in that the step in which a plurality of charge carriers corresponds to the input signal is added to the precharge comprises first adding a larger amount of such such carriers to the input potential group and then, in response to the input signal, offset sufficient number of charge carriers from the input potential pit, to leave in the potential pit a number corresponding to the sum of the precharge and a to the input signal proportional number.