CA1101994A - Linear ccd input circuit - Google Patents
Linear ccd input circuitInfo
- Publication number
- CA1101994A CA1101994A CA293,993A CA293993A CA1101994A CA 1101994 A CA1101994 A CA 1101994A CA 293993 A CA293993 A CA 293993A CA 1101994 A CA1101994 A CA 1101994A
- Authority
- CA
- Canada
- Prior art keywords
- charge
- electrode
- potential well
- input
- ccd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012546 transfer Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 29
- 239000002800 charge carrier Substances 0.000 claims description 12
- 230000004044 response Effects 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 4
- 230000001902 propagating effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 3
- 230000000644 propagated effect Effects 0.000 description 3
- 238000013519 translation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
- G11C19/285—Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76808—Input structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Abstract of the Disclosure Linear operation of a buried channel charge coupled device (CCD) is obtained by employing a bias charge in the input potential well of the CCD. A charge signal proportional to an input signal is added to the bias charge by the "fill and spill" technique, this charge addition occurring in the linear region of the signal versus generated charge transfer characteristic of the CCD. The charge signal is skimmed from the potential well for propagation down the CCD. The potential well containing the bias charge is of substantially larger capacity than the potential wells of the CCD channel to insure that the latter can be fill to close to their capacity, that is, to obtain wide dynamic range in addition to the linear operation.
Description
, R.CA 71,287 1 The present invention is directed to an improved charge coupled device (~n) and particularly to the input circuit for such a device.
A charge coupled device, accordin~ to the prior art, comprises a substrate and electrodes insulated from the substrate. Multiple phase volta~es applied to the electrodes form potential wells in the substrate for the storage and propagate charge signals along the length of the channel. The charge coupled device also ; 10 includes a source electrode in the substrate. F.lectrode means insulated from the substrate and located between the source electrode and the CCD channel are responsive to an input signal, for controlling the introduction of charge from the source electrode to the CCD channel.
According to the invention, the electrode means ; includes storage electrode means for for~ing an input potential well in the substrate in response to an applied voltage which input potential well is substantially larger than the capacity of the potential wells in the CCD channel. The input potential well has a signal voltage versus number-of-charge-carriers-introduced transfer function, which is relatively non-linear at lower input signal levels and relatively linear at higher input signal levels. In order to overcome the problem presented by this nonlinear transfer function, there is proved ~ ;
means responsive to the input signal and to a control voltage manifestation for introducing into the input potential well a charge which includes a bias component at a level which corresponds to the non-linear region of said transfer characteristic and further includes a . ~ ~
A charge coupled device, accordin~ to the prior art, comprises a substrate and electrodes insulated from the substrate. Multiple phase volta~es applied to the electrodes form potential wells in the substrate for the storage and propagate charge signals along the length of the channel. The charge coupled device also ; 10 includes a source electrode in the substrate. F.lectrode means insulated from the substrate and located between the source electrode and the CCD channel are responsive to an input signal, for controlling the introduction of charge from the source electrode to the CCD channel.
According to the invention, the electrode means ; includes storage electrode means for for~ing an input potential well in the substrate in response to an applied voltage which input potential well is substantially larger than the capacity of the potential wells in the CCD channel. The input potential well has a signal voltage versus number-of-charge-carriers-introduced transfer function, which is relatively non-linear at lower input signal levels and relatively linear at higher input signal levels. In order to overcome the problem presented by this nonlinear transfer function, there is proved ~ ;
means responsive to the input signal and to a control voltage manifestation for introducing into the input potential well a charge which includes a bias component at a level which corresponds to the non-linear region of said transfer characteristic and further includes a . ~ ~
-2- . P
~- .
` RCA 71,287 ~101994 l signal component. Also provided is means for removin~
from said input potential well beneath the stora~e electrode the signal component of the charge stored therein and for propagating that signal component to the CCD channel, while retaining in the input potential well beneath the storage electrode the bias component of the charge.
In the drawings:
FIGURE 1 is a graph of input signal voltage-versus-charge carriers produced, in a conventionally onerated buried channel CCD input stage;
FI~UR~ 2 is a plan view of a CC~ input circuit embodying the present invention;
FIGURE 3 is a section taken along line 3-3 of FIGURE 2;
PIGURE 4 is a drawing of substrate potential profiles to help explain the operation of the circuit of FIGURES 2 and 3;
FIGllRE ~ is a drawing of waveform ti~ing employed in the operation of the circuit of FIGURES 2 and
~- .
` RCA 71,287 ~101994 l signal component. Also provided is means for removin~
from said input potential well beneath the stora~e electrode the signal component of the charge stored therein and for propagating that signal component to the CCD channel, while retaining in the input potential well beneath the storage electrode the bias component of the charge.
In the drawings:
FIGURE 1 is a graph of input signal voltage-versus-charge carriers produced, in a conventionally onerated buried channel CCD input stage;
FI~UR~ 2 is a plan view of a CC~ input circuit embodying the present invention;
FIGURE 3 is a section taken along line 3-3 of FIGURE 2;
PIGURE 4 is a drawing of substrate potential profiles to help explain the operation of the circuit of FIGURES 2 and 3;
FIGllRE ~ is a drawing of waveform ti~ing employed in the operation of the circuit of FIGURES 2 and
3; and FIGURES 6a and 6b are ~raphs to help explain the operation of the circuits of PI~IlR~S 2 and 3.
U.S. Patent No. 3,986,198 issued October 12, 197fi to Walter P. Kosonocky describes relatively noise-free circuits for introducing a charge signal into a CCD
register. The technique employed has become known as the "fill and spill" mode of operation. Charge signals is , introduced from a source electrode to a first potential ,, 30 -2a-RCA 71,287 llQ~ggg 1 well, this being the fill portion of the cycle. Then, the potential well is partially emptied, for example by operating the source electrode as a drain. nuring the emptying process, an input signal potential is maintained between the electrode under which the potential . well is formed and a second electrode between that electrode and the source electrode. The char~e which remains in the first potential well is a function of the amplitude of this --~
' 10 / ':
' ' / '~/ ~ ;
2~ /
'.'; ' / - . :~ ~
/ .
;
-2b-.- - . , , .. . , ~ . , RCA 71,287 ~0~994 I input signal and is relatively noise free.
It has been found that when the CCD is a buried channel CCD, the operation described above, while relatively noise free, results in relatively non-linear translation of the input signal to charge (as compared to the signal translation which occurs in a surface channel CCD). The transfer characteristic of signal voltage versus number of charge carriers produced for a typical buried N-channel CCD, is shown in FIGURE 1. The flat region 11 at the top represents the charge capacity of the input potential well and it may be slightly greater than that of each transfer potential well along the major part of the CCD channel. The capacity of such a transfer potential well is represented by dashed line 13.
The curve includes a relatively non-linear region at relatively low signal levels (between Vz volts and Vx) and a relatively linear region at relatively high signal levels (between Vx and Vy). A change in signal level ~VINl at a relatively low input ~ignal level i8 translated non-linearly to a charge signal in the input potential well; a change in input signal ~VIN2 at a relatively high input signal level is translated linearly to a charge signal in the input potential well. The non-linear region results, for example, from the characteristic of a buried channel device that the capacitance of the buried channel varies more as a function of charge level at lower value~ of charge than at higher values of charge. There are also more complex effects which influence the degree of non-linearity.
In certain applications as, for example, in CCD
delay lines employed to delay analog signals such as the -3- , :- ~ : . -.
: .
- , ~ RCA 71,287 9~4 I video signals of television, operation as discussed above is, of course, highly disadvantageous. It is desirable that the CCD delay line introduce as little distortion as possible to the analog signal and to do this, the input circuit to the CCD should operate in linear fashion.
It is also important that a CCD delay line as described above not occupy excessive area on the semiconductor substrate. The CCD is designed to have a channel width and electrode areas such that the potential wells which are formed in response to the multiple phase voltages can store only as much charge as can be produced by the greatest amplitude input signal expected (assuming some practical value such as 10-12 volts or so of multiple phase voltage). If the CCD
; electrode areas are ~ade larger, it means that each CCD delay line is larger and this, in turn, means that fewer such CCD
delay lines can be obtained from a single wafer~n practice, many delay lines are,fabricated at the same time on the same uae~ and are then cleaved or separated in some other way from one another). This is wasteful and adds to the expense of 20 each line. In addition, larger area delay linee exhibit -' greater capacitance and this makes operating them at high frequencie~ (high fre~uency multiple phase voltages) more difficult and reauires greater power dissipation in the CCD
driver circuits.
FIGURÉS 2 and 3 illustrate a circuit embodying the invention which solves the problems above. The CCD includes a P-type silicon substrate 10 and a source electrode S at the substrate surface. This source electrode may comprise an N-type diffusion in the P-type substrate. The layer B comprises a thin layer of N-type silicon at the substrat~ surface and .
.
RCA 71,287 .
1 forming a PN junction 12 with the substrate. Layer B, as is well understood in the art, is less highly doped than the source diffusion S. The CCD input electrodes comprise three gate electrodes Gl, G2 and G3, in that order, followed by multiple phase electrodes 14, 16, 18, 20 and so on. By way of illustration, these electrodes may all be formed of polysilicon and may be the overlapped, two-layer type. Of course other materials and other forms of construction are possible and within the scope of the present invention. The CCD channel, which may be defined by channel stop diffusions ~not shown), is r~latively wide beneath the input electrodes Gl, G2 and G3 and tapers down to a narrower width for the major part of the CCD as illustrated by dashed lines. This major part of the CCD (not shown) may include several hundred CCD stages (over 500 in one practical design, with four electrodes, per stage). In the embodiment illustrated, the wider portion of the CCD channel may have a width double that of the major portion of the CCD channel as indicated by the widths 2w and w, respectively, in FIGURE 2.
The operation of the CCD is depicted in FIGURES 4 and 5. It iB assumed for purposes of illustration that at time to~ no charge is present in the potential well 26 beneath electrode G2 as indicated at a of FIGURE 4. At this time, ~1 ;
~ is low so that there is a potential barrier 20 beneath the ',~ 25 first ~1 electrode 14 and a shallow potential well 22 beneath the electrode 16. The shallow well occurs because electrode ~ ,......................................................... .
16 is maintained at a direct voltage offset which is relatively ; positive compared to the voltage at electrode 14. This is indicated schematically by the battery 15. V3 is at a relatively low level at this time so there is a potential .~
RCA 71,287 ~ 0:~.994 1 barrier 24 beneath electrode G3. V~ continuously is maintained at a relatively high dc level so that a potential well 26 is present beneath storage electrode G2. This well may be considered the "input" potential well. Vl also is a dc level but it is less positive than V2. This voltage and the signal ~oltage VIN are applied to electrode Gl. Accordingly, there is continuous~y present beneath electrode Gl a potential barrier whose height is a function of the dc level Vl plus the oignal level VIN. The voltage V~ is relatively positive at time to so that diffusion ~ acts as a drain for charge carriers.
At time tl, the voltage Vs i3 relatively negative ; so that the diffusion S operates as a source of charge carriers. These charge carriers ~electrons) now fill the potential well 26 to the level 30.
At time t2, the voltage Vs is at its more positive value, causing the diffusion S to operate as a drain. Now some of the charge pre~ent in well 26 spill8 back over the barrier 28 and into region ~. The charge remaining in potential well 26 includes one component proportional to - signal and another proportional to the difference in dc levels between Vl and V2. In the drawing, the charge in well 26 i~ cros8-hatched in two different ways. One part 32 of this charge will continuously remain in this well and it is legended "bias." The remainder 34 of the charge, legended "signal" will be "skimmed" from the well and propagated down the CCD register as will be explained shortly.
At time t3, V3 is relatively positive so that the height of barrier 24 is substantially lower than it was at time t2. The voltage V2 applied to the storage electrode G2 ~ -6-.
- .
~. ~ '-' ' ;
RCA 71,287 ~0199i4 1 remains the same, as already mentioned. At time t3 also, the PHASE 1 voltage ~1 is high so that potential wells 36 and 38 are present beneath, the ~l electrodes 14 and 16, respectively.
As electrode 16 is biased more positively than electrode 14, the well 38 beneath electrode 16 is deeper than the well 36 beneath electrod,e 14.' (While for purposes of the present discussion a means 15 providing a voltage offset between two electrodes is shown for producing an asymmetrical potential well, alternative structures are possible. One is to employ a single electrode in place of the two such as 14, 16 and to employ a suitable ion implant under one of them.) The ~1 voltage is of substa~tially greater amplitude than the V3 voltage at time t3 so that well potential 20 is higher than (appears as a potential well relative to) well potential 24.
In responoe to these co~ditions, a portion of the charge ~, in potential well 26 is skimmed from this well and propagated '~ to well 38. The remainder of the charge, the bias charge 32, ', continues to remain in potential well 26. The portion 34 of the charge formerly in well 26 and now in well 38 subs'equently is propagated down the CCD register by the two ,......................................................................... .
";,, phase voltages ~ 2 i~ conventional fashion.
;;',l The significance of the operation in the way ',l described may be better appreciated by referring to FIGURE
~ 6a. This graph is drawn to smaller scale than FIGURE 1 ,'j 25 tassuming dashed line 13 represents the same charge level , in both figures, note that this dashed line is roughly twice '~ as far from the zero charge level than the same line in FIGUR~ 6a) but the same reference numerals are employed to describe similar parts of the graph. The potential well 26 30 (FIG . 4) continuously RCA 71,287 1 retains a bias charge (32 of FIGURE 4) which is represented by the dashed line 15 of FIGURE 6. Thi~ dashed line defines the start of the relatively linear region of the transfer curve. Any charge added to this potential well in response to an input signal VIN results in substantially linear translation of this input signal to charge (34 of FIGURE 4) because the opera~ion is in the linear region of the characteristic. Moreover, the structure is such that full dynamic range is obtained. In other word~, because the input potential well (the well beneath electrode G2) is in a region where the channel is wide, its capacity is relatively large--approximately double that of the CCD transfer wells in the major part of the'CCD (the input well beneath electrode G2 has approximately double the capacity of a well beneath an electrode s,uch as 42 of FIGURES 2 and 3). This means that , even though the potential well 26 beneath storage electrode ', G2 is available to accept signal charge up to only a fraction of its capacity (assume that when the input signal is at its maximum value, it occupies only one half the well, the bias charge occupying the remainder of the well), the charge 8ignal skimmed from this potential well 26 still can fill the well beneath electrode 42 to substantially its entire capacity, at maximum input signal level, Thus, the CCD
~ described operates linearly over substantially the full '~ 25 capacity of the transfer potential wells in the body of the CCD and therefore has wider useful dynamic range.
The tranRfer function of a typical transfer potential well such as one beneath electrode 42 of FIGS. 2 and 3 as ~' related to the input signal VIN applied to electrode G, is illustrated -in FIGURE 6b. The full transfer well capacity is illustrated at 13. Note that the operation is quite linear , RCA 71,287 1~0~994 .
1 over almost the entire characteristic. (It is found, in practice, that at extremely low input signal VIN levels, some minor non-linearity is introduced as shown at 17, but the reason is not yet fully understood.) The substantially linear operation described above is achieved without requiring ex~essive substrate area. In one practical design, the major part of the CCD comprises over 500 stages (over 2,000 electrodes) and the channel width, electrode areas and substrate areas of all except the first of these stages remain unchanged. The electrodes 14, 16, 18, 20 of this first stage are increased in area, one additional gate eleatrode G3 is employed an~ the source electrode and first two gate electrodes are increased in area. The total ! . increase in size required of the CCD is not significant--only i 15 a fraction of a percent.
, While for purposes of illustration two phase operation ~l ~ is assumed, it is of course to be appreciated that the ;~ invention is equally applicable to three, four or higher phase operation. It is also to be understood that while the CCD
illustrated employs a P-type sub8trate, it is equally applicable ; to N-type substrate devices employing P-type surface layers and a P-type source region. Of course, appropriate changes , . .
in operating voltages are re~uired. Further, while typical ~- waveforms are illustrated, modifications are possible. For example, the voltage V3 is shown to have the same shape as the wave ~1 ~owever, proper operation can still be obtained with V3 of different shape than Vl. V3 should be low at the time Vs is low, however, V3 can go high before ~1 goes hig~.
~hile not illustrated, the system disclosed can employ the technique illustrated in either of two copcnding-_g_ - ~ -.
~ ~ RCA 71,287 l United States patents identified below for insuring that the source electrode operates at proper potentials during the fill and spill operation. These are United States Patent No. 4,191,895 granted to Peter A. Levine and Donald J. Sauer for "Low Noise CCD Input Circuit" and United States Patent No. 4,191,896 granted to Donald J. Sauer and Peter A. Levine for "Low Noise CCD Input Circuit." Both of these patents are assigned to the same assignee as the present application.
,' , ~ 20 '' ' ;'''~:
-lO-,
U.S. Patent No. 3,986,198 issued October 12, 197fi to Walter P. Kosonocky describes relatively noise-free circuits for introducing a charge signal into a CCD
register. The technique employed has become known as the "fill and spill" mode of operation. Charge signals is , introduced from a source electrode to a first potential ,, 30 -2a-RCA 71,287 llQ~ggg 1 well, this being the fill portion of the cycle. Then, the potential well is partially emptied, for example by operating the source electrode as a drain. nuring the emptying process, an input signal potential is maintained between the electrode under which the potential . well is formed and a second electrode between that electrode and the source electrode. The char~e which remains in the first potential well is a function of the amplitude of this --~
' 10 / ':
' ' / '~/ ~ ;
2~ /
'.'; ' / - . :~ ~
/ .
;
-2b-.- - . , , .. . , ~ . , RCA 71,287 ~0~994 I input signal and is relatively noise free.
It has been found that when the CCD is a buried channel CCD, the operation described above, while relatively noise free, results in relatively non-linear translation of the input signal to charge (as compared to the signal translation which occurs in a surface channel CCD). The transfer characteristic of signal voltage versus number of charge carriers produced for a typical buried N-channel CCD, is shown in FIGURE 1. The flat region 11 at the top represents the charge capacity of the input potential well and it may be slightly greater than that of each transfer potential well along the major part of the CCD channel. The capacity of such a transfer potential well is represented by dashed line 13.
The curve includes a relatively non-linear region at relatively low signal levels (between Vz volts and Vx) and a relatively linear region at relatively high signal levels (between Vx and Vy). A change in signal level ~VINl at a relatively low input ~ignal level i8 translated non-linearly to a charge signal in the input potential well; a change in input signal ~VIN2 at a relatively high input signal level is translated linearly to a charge signal in the input potential well. The non-linear region results, for example, from the characteristic of a buried channel device that the capacitance of the buried channel varies more as a function of charge level at lower value~ of charge than at higher values of charge. There are also more complex effects which influence the degree of non-linearity.
In certain applications as, for example, in CCD
delay lines employed to delay analog signals such as the -3- , :- ~ : . -.
: .
- , ~ RCA 71,287 9~4 I video signals of television, operation as discussed above is, of course, highly disadvantageous. It is desirable that the CCD delay line introduce as little distortion as possible to the analog signal and to do this, the input circuit to the CCD should operate in linear fashion.
It is also important that a CCD delay line as described above not occupy excessive area on the semiconductor substrate. The CCD is designed to have a channel width and electrode areas such that the potential wells which are formed in response to the multiple phase voltages can store only as much charge as can be produced by the greatest amplitude input signal expected (assuming some practical value such as 10-12 volts or so of multiple phase voltage). If the CCD
; electrode areas are ~ade larger, it means that each CCD delay line is larger and this, in turn, means that fewer such CCD
delay lines can be obtained from a single wafer~n practice, many delay lines are,fabricated at the same time on the same uae~ and are then cleaved or separated in some other way from one another). This is wasteful and adds to the expense of 20 each line. In addition, larger area delay linee exhibit -' greater capacitance and this makes operating them at high frequencie~ (high fre~uency multiple phase voltages) more difficult and reauires greater power dissipation in the CCD
driver circuits.
FIGURÉS 2 and 3 illustrate a circuit embodying the invention which solves the problems above. The CCD includes a P-type silicon substrate 10 and a source electrode S at the substrate surface. This source electrode may comprise an N-type diffusion in the P-type substrate. The layer B comprises a thin layer of N-type silicon at the substrat~ surface and .
.
RCA 71,287 .
1 forming a PN junction 12 with the substrate. Layer B, as is well understood in the art, is less highly doped than the source diffusion S. The CCD input electrodes comprise three gate electrodes Gl, G2 and G3, in that order, followed by multiple phase electrodes 14, 16, 18, 20 and so on. By way of illustration, these electrodes may all be formed of polysilicon and may be the overlapped, two-layer type. Of course other materials and other forms of construction are possible and within the scope of the present invention. The CCD channel, which may be defined by channel stop diffusions ~not shown), is r~latively wide beneath the input electrodes Gl, G2 and G3 and tapers down to a narrower width for the major part of the CCD as illustrated by dashed lines. This major part of the CCD (not shown) may include several hundred CCD stages (over 500 in one practical design, with four electrodes, per stage). In the embodiment illustrated, the wider portion of the CCD channel may have a width double that of the major portion of the CCD channel as indicated by the widths 2w and w, respectively, in FIGURE 2.
The operation of the CCD is depicted in FIGURES 4 and 5. It iB assumed for purposes of illustration that at time to~ no charge is present in the potential well 26 beneath electrode G2 as indicated at a of FIGURE 4. At this time, ~1 ;
~ is low so that there is a potential barrier 20 beneath the ',~ 25 first ~1 electrode 14 and a shallow potential well 22 beneath the electrode 16. The shallow well occurs because electrode ~ ,......................................................... .
16 is maintained at a direct voltage offset which is relatively ; positive compared to the voltage at electrode 14. This is indicated schematically by the battery 15. V3 is at a relatively low level at this time so there is a potential .~
RCA 71,287 ~ 0:~.994 1 barrier 24 beneath electrode G3. V~ continuously is maintained at a relatively high dc level so that a potential well 26 is present beneath storage electrode G2. This well may be considered the "input" potential well. Vl also is a dc level but it is less positive than V2. This voltage and the signal ~oltage VIN are applied to electrode Gl. Accordingly, there is continuous~y present beneath electrode Gl a potential barrier whose height is a function of the dc level Vl plus the oignal level VIN. The voltage V~ is relatively positive at time to so that diffusion ~ acts as a drain for charge carriers.
At time tl, the voltage Vs i3 relatively negative ; so that the diffusion S operates as a source of charge carriers. These charge carriers ~electrons) now fill the potential well 26 to the level 30.
At time t2, the voltage Vs is at its more positive value, causing the diffusion S to operate as a drain. Now some of the charge pre~ent in well 26 spill8 back over the barrier 28 and into region ~. The charge remaining in potential well 26 includes one component proportional to - signal and another proportional to the difference in dc levels between Vl and V2. In the drawing, the charge in well 26 i~ cros8-hatched in two different ways. One part 32 of this charge will continuously remain in this well and it is legended "bias." The remainder 34 of the charge, legended "signal" will be "skimmed" from the well and propagated down the CCD register as will be explained shortly.
At time t3, V3 is relatively positive so that the height of barrier 24 is substantially lower than it was at time t2. The voltage V2 applied to the storage electrode G2 ~ -6-.
- .
~. ~ '-' ' ;
RCA 71,287 ~0199i4 1 remains the same, as already mentioned. At time t3 also, the PHASE 1 voltage ~1 is high so that potential wells 36 and 38 are present beneath, the ~l electrodes 14 and 16, respectively.
As electrode 16 is biased more positively than electrode 14, the well 38 beneath electrode 16 is deeper than the well 36 beneath electrod,e 14.' (While for purposes of the present discussion a means 15 providing a voltage offset between two electrodes is shown for producing an asymmetrical potential well, alternative structures are possible. One is to employ a single electrode in place of the two such as 14, 16 and to employ a suitable ion implant under one of them.) The ~1 voltage is of substa~tially greater amplitude than the V3 voltage at time t3 so that well potential 20 is higher than (appears as a potential well relative to) well potential 24.
In responoe to these co~ditions, a portion of the charge ~, in potential well 26 is skimmed from this well and propagated '~ to well 38. The remainder of the charge, the bias charge 32, ', continues to remain in potential well 26. The portion 34 of the charge formerly in well 26 and now in well 38 subs'equently is propagated down the CCD register by the two ,......................................................................... .
";,, phase voltages ~ 2 i~ conventional fashion.
;;',l The significance of the operation in the way ',l described may be better appreciated by referring to FIGURE
~ 6a. This graph is drawn to smaller scale than FIGURE 1 ,'j 25 tassuming dashed line 13 represents the same charge level , in both figures, note that this dashed line is roughly twice '~ as far from the zero charge level than the same line in FIGUR~ 6a) but the same reference numerals are employed to describe similar parts of the graph. The potential well 26 30 (FIG . 4) continuously RCA 71,287 1 retains a bias charge (32 of FIGURE 4) which is represented by the dashed line 15 of FIGURE 6. Thi~ dashed line defines the start of the relatively linear region of the transfer curve. Any charge added to this potential well in response to an input signal VIN results in substantially linear translation of this input signal to charge (34 of FIGURE 4) because the opera~ion is in the linear region of the characteristic. Moreover, the structure is such that full dynamic range is obtained. In other word~, because the input potential well (the well beneath electrode G2) is in a region where the channel is wide, its capacity is relatively large--approximately double that of the CCD transfer wells in the major part of the'CCD (the input well beneath electrode G2 has approximately double the capacity of a well beneath an electrode s,uch as 42 of FIGURES 2 and 3). This means that , even though the potential well 26 beneath storage electrode ', G2 is available to accept signal charge up to only a fraction of its capacity (assume that when the input signal is at its maximum value, it occupies only one half the well, the bias charge occupying the remainder of the well), the charge 8ignal skimmed from this potential well 26 still can fill the well beneath electrode 42 to substantially its entire capacity, at maximum input signal level, Thus, the CCD
~ described operates linearly over substantially the full '~ 25 capacity of the transfer potential wells in the body of the CCD and therefore has wider useful dynamic range.
The tranRfer function of a typical transfer potential well such as one beneath electrode 42 of FIGS. 2 and 3 as ~' related to the input signal VIN applied to electrode G, is illustrated -in FIGURE 6b. The full transfer well capacity is illustrated at 13. Note that the operation is quite linear , RCA 71,287 1~0~994 .
1 over almost the entire characteristic. (It is found, in practice, that at extremely low input signal VIN levels, some minor non-linearity is introduced as shown at 17, but the reason is not yet fully understood.) The substantially linear operation described above is achieved without requiring ex~essive substrate area. In one practical design, the major part of the CCD comprises over 500 stages (over 2,000 electrodes) and the channel width, electrode areas and substrate areas of all except the first of these stages remain unchanged. The electrodes 14, 16, 18, 20 of this first stage are increased in area, one additional gate eleatrode G3 is employed an~ the source electrode and first two gate electrodes are increased in area. The total ! . increase in size required of the CCD is not significant--only i 15 a fraction of a percent.
, While for purposes of illustration two phase operation ~l ~ is assumed, it is of course to be appreciated that the ;~ invention is equally applicable to three, four or higher phase operation. It is also to be understood that while the CCD
illustrated employs a P-type sub8trate, it is equally applicable ; to N-type substrate devices employing P-type surface layers and a P-type source region. Of course, appropriate changes , . .
in operating voltages are re~uired. Further, while typical ~- waveforms are illustrated, modifications are possible. For example, the voltage V3 is shown to have the same shape as the wave ~1 ~owever, proper operation can still be obtained with V3 of different shape than Vl. V3 should be low at the time Vs is low, however, V3 can go high before ~1 goes hig~.
~hile not illustrated, the system disclosed can employ the technique illustrated in either of two copcnding-_g_ - ~ -.
~ ~ RCA 71,287 l United States patents identified below for insuring that the source electrode operates at proper potentials during the fill and spill operation. These are United States Patent No. 4,191,895 granted to Peter A. Levine and Donald J. Sauer for "Low Noise CCD Input Circuit" and United States Patent No. 4,191,896 granted to Donald J. Sauer and Peter A. Levine for "Low Noise CCD Input Circuit." Both of these patents are assigned to the same assignee as the present application.
,' , ~ 20 '' ' ;'''~:
-lO-,
Claims (7)
1. A method of operating a CCD of the type which has an input potential well transfer function of number of charge carriers produced versus input signal voltage which is relatively non-linear in a first input signal range between first and second signal levels, V1 and V2, respectively and which is relatively linear in a second input signal range between said second level V2 and a third signal level V3, where the first, second and third levels are of successively higher values, the steps of:
placing a bias charge in said input potential well at a level corresponding to the number of charge carriers which would be produced in response to an input signal at substantially said second signal level V2;
adding to said bias charge in said input potential well, a number of charge carriers proportional to an input signal whose amplitude is in the range of zero to (V3- V2);
skimming from said potential well only that portion of the charge therein which exceeds said bias charge signal; and transmitting said skimmed charge along the length of said CCD by propagating the same in potential wells of substantially smaller capacity than said input potential well but still of sufficient capacity to store a charge corresponding to the maximum input signal level V3- V2.
RCA 71,287
placing a bias charge in said input potential well at a level corresponding to the number of charge carriers which would be produced in response to an input signal at substantially said second signal level V2;
adding to said bias charge in said input potential well, a number of charge carriers proportional to an input signal whose amplitude is in the range of zero to (V3- V2);
skimming from said potential well only that portion of the charge therein which exceeds said bias charge signal; and transmitting said skimmed charge along the length of said CCD by propagating the same in potential wells of substantially smaller capacity than said input potential well but still of sufficient capacity to store a charge corresponding to the maximum input signal level V3- V2.
RCA 71,287
2. The method of claim 1, wherein the step of adding to said bias charge a number of charge carriers proportional to said input signal comprises first adding a greater number of such charge carriers to said input potential well and then, in response to said input signal, removing from said input potential well a sufficient number of charge carriers to leave stored in said well a number corresponding to said bias charge plus the number proportional to said input signal.
3. In a charge coupled device which includes a CCD channel comprising a substrate and electrodes insulated from the substrate to which multiple phase voltages may be applied for forming potential wells in the substrate for the storage and propagation of charge signals along the length of said channel and which also includes a source electrode in the substrate and electrode means insulated from the substrate and located between the source electrode and the CCD channel responsive to an input signal for controlling the introduction of charge from said source electrode to said CCD channel, the improvement comprising:
said electrode means including storage electrode means for forming an input potential well in said substrate in response to an applied voltage which input potential well is substantially larger than the capacity of the potential wells in said CCD channel, said input potential well having a signal voltage versus number of charge carriers introduced transfer function which is relatively non-linear at lower input signal levels and relatively RCA 71,287
3. In a charge coupled device which includes a CCD channel comprising a substrate and electrodes insulated from the substrate to which multiple phase voltages may be applied for forming potential wells in the substrate for the storage and propagation of charge signals along the length of said channel and which also includes a source electrode in the substrate and electrode means insulated from the substrate and located between the source electrode and the CCD channel responsive to an input signal for controlling the introduction of charge from said source electrode to said CCD channel, the improvement comprising:
said electrode means including storage electrode means for forming an input potential well in said substrate in response to an applied voltage which input potential well is substantially larger than the capacity of the potential wells in said CCD channel, said input potential well having a signal voltage versus number of charge carriers introduced transfer function which is relatively non-linear at lower input signal levels and relatively RCA 71,287
Claim 3 continued linear at higher input signal levels;
means responsive to said input signal and a control voltage manifestation for introducing into said potential well a charge which includes a bias component at a level corresponding to the non-linear region of said transfer characteristic and a signal component; and means for removing from said input potential well beneath said storage electrode the signal component of the charge stored therein and propagating the same to said CCD channel while retaining the bias component of said charge in said potential well beneath said storage electrode.
means responsive to said input signal and a control voltage manifestation for introducing into said potential well a charge which includes a bias component at a level corresponding to the non-linear region of said transfer characteristic and a signal component; and means for removing from said input potential well beneath said storage electrode the signal component of the charge stored therein and propagating the same to said CCD channel while retaining the bias component of said charge in said potential well beneath said storage electrode.
4. The charge coupled device set forth in claim 3 wherein said charge coupled device comprises a buried channel charge coupled device.
5. The charge coupled device set forth in claim 4 wherein said means responsive to said input signal and said control voltage manifestation comprises:
a control electrode to which said signal is applied, said control electrode being insulated from the substrate and located between said storage electrode and said source electrode; and said control voltage manifestation is applied between said source electrode and said control electrode at one value during one interval of time for filling said potential well beneath said storage electrode with charge and being applied at another value during a RCA 71,287
5. The charge coupled device set forth in claim 4 wherein said means responsive to said input signal and said control voltage manifestation comprises:
a control electrode to which said signal is applied, said control electrode being insulated from the substrate and located between said storage electrode and said source electrode; and said control voltage manifestation is applied between said source electrode and said control electrode at one value during one interval of time for filling said potential well beneath said storage electrode with charge and being applied at another value during a RCA 71,287
Claim 5 continued following interval of time for removing a portion of said charge, thereby to leave in said potential well said charge which includes said signal component and said bias component.
6. The charge coupled device as set forth in claim 3 wherein said electrode means includes storage electrode means for making the depth of said input potential well at least double the size of the potential wells in said CCD channel.
7. A charge coupled device input circuit comprising:
a semiconductor substrate;
a source electrode in said substrate;
a CCD buried channel ("CCD CHANNEL") is said substrate comprising a first region (left-hand end, width 2W) adjacent to said source electrode, a substantially narrower third region (right-hand end, width W) comprising the major portion of the CCD, and a second tapering region which joins the input and third regions;
first? second and third electrodes over said first region and insulated from said substrate, said second electrode comprising a storage electrode, said first electrode being located between said storage electrode and said source electrode, and said third electrode being located between said second electrode and said second region of said CCD channel;
RCA 71,287
7. A charge coupled device input circuit comprising:
a semiconductor substrate;
a source electrode in said substrate;
a CCD buried channel ("CCD CHANNEL") is said substrate comprising a first region (left-hand end, width 2W) adjacent to said source electrode, a substantially narrower third region (right-hand end, width W) comprising the major portion of the CCD, and a second tapering region which joins the input and third regions;
first? second and third electrodes over said first region and insulated from said substrate, said second electrode comprising a storage electrode, said first electrode being located between said storage electrode and said source electrode, and said third electrode being located between said second electrode and said second region of said CCD channel;
RCA 71,287
Claim 7 continued means for applying a voltage to said second electrode for creating a potential well in said substrate;
means for applying an input signal to said first electrode;
means for applying a difference in potential between said source and first electrodes of a value to fill said potential well with charge and then of a value to spill some of said charge back into said source electrode, to leave in said well a charge which includes a signal component and a bias component, said bias component occupying a substantial portion of said well;
means for maintaining said third electrode at a potential to form a barrier in said substrate during at least the period said potential well is being filled;
electrodes over said third region responsive to multiple phase voltages for creating potential wells in the substrate of substantially smaller capacity than the potential well beneath said second electrode but of sufficient capacity to store and propagate said signal component;
means for changing the potential applied to said third electrode to a value such that that portion of the charge in said potential well beneath said second electrode, which portion exceeds said bias level, can flow over the reduced potential barrier beneath said third electrode;
and means in said second region of said CCD channel for transferring said charge which flows over said reduced potential barrier to said third region of said channel.
means for applying an input signal to said first electrode;
means for applying a difference in potential between said source and first electrodes of a value to fill said potential well with charge and then of a value to spill some of said charge back into said source electrode, to leave in said well a charge which includes a signal component and a bias component, said bias component occupying a substantial portion of said well;
means for maintaining said third electrode at a potential to form a barrier in said substrate during at least the period said potential well is being filled;
electrodes over said third region responsive to multiple phase voltages for creating potential wells in the substrate of substantially smaller capacity than the potential well beneath said second electrode but of sufficient capacity to store and propagate said signal component;
means for changing the potential applied to said third electrode to a value such that that portion of the charge in said potential well beneath said second electrode, which portion exceeds said bias level, can flow over the reduced potential barrier beneath said third electrode;
and means in said second region of said CCD channel for transferring said charge which flows over said reduced potential barrier to said third region of said channel.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US75818477A | 1977-01-10 | 1977-01-10 | |
| US758,184 | 1977-01-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1101994A true CA1101994A (en) | 1981-05-26 |
Family
ID=25050832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA293,993A Expired CA1101994A (en) | 1977-01-10 | 1977-12-28 | Linear ccd input circuit |
Country Status (16)
| Country | Link |
|---|---|
| JP (2) | JPS5387675A (en) |
| AU (1) | AU511885B2 (en) |
| BE (1) | BE862760A (en) |
| CA (1) | CA1101994A (en) |
| DE (1) | DE2800893C2 (en) |
| DK (1) | DK149674C (en) |
| ES (1) | ES465682A1 (en) |
| FI (1) | FI72410C (en) |
| FR (1) | FR2377127A1 (en) |
| GB (1) | GB1579033A (en) |
| IT (1) | IT1089179B (en) |
| NL (1) | NL7800272A (en) |
| NZ (1) | NZ186177A (en) |
| PL (1) | PL120630B1 (en) |
| SE (1) | SE437438B (en) |
| ZA (1) | ZA7810B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4139784A (en) * | 1977-08-02 | 1979-02-13 | Rca Corporation | CCD Input circuits |
| US4158209A (en) * | 1977-08-02 | 1979-06-12 | Rca Corporation | CCD comb filters |
| US4217605A (en) * | 1978-08-02 | 1980-08-12 | Rca Corporation | Comb filter employing a charge transfer device with plural mutually proportioned signal charge inputs |
| JPS5528523A (en) * | 1978-08-17 | 1980-02-29 | Toshiba Corp | Signal charge input system for charge transfer element |
| DE2836473A1 (en) * | 1978-08-21 | 1980-03-06 | Siemens Ag | CCD INPUT SWITCHING AFTER THE FILL AND SPILL PRINCIPLE |
| DE3138946A1 (en) * | 1981-09-30 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | Method for operating a charge transfer device provided with a preceding low-pass filter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3986198A (en) * | 1973-06-13 | 1976-10-12 | Rca Corporation | Introducing signal at low noise level to charge-coupled circuit |
| JPS5416838B2 (en) * | 1973-11-29 | 1979-06-25 |
-
1977
- 1977-01-04 AU AU32166/78A patent/AU511885B2/en not_active Expired
- 1977-12-21 IT IT31058/77A patent/IT1089179B/en active
- 1977-12-28 CA CA293,993A patent/CA1101994A/en not_active Expired
-
1978
- 1978-01-03 ES ES465682A patent/ES465682A1/en not_active Expired
- 1978-01-03 FI FI780012A patent/FI72410C/en not_active IP Right Cessation
- 1978-01-03 ZA ZA00780010A patent/ZA7810B/en unknown
- 1978-01-04 SE SE7800104A patent/SE437438B/en not_active IP Right Cessation
- 1978-01-05 GB GB342/78A patent/GB1579033A/en not_active Expired
- 1978-01-09 BE BE184205A patent/BE862760A/en not_active IP Right Cessation
- 1978-01-09 NZ NZ186177A patent/NZ186177A/en unknown
- 1978-01-09 DK DK8878A patent/DK149674C/en not_active IP Right Cessation
- 1978-01-09 NL NL7800272A patent/NL7800272A/en not_active Application Discontinuation
- 1978-01-09 JP JP106078A patent/JPS5387675A/en active Granted
- 1978-01-10 FR FR7800570A patent/FR2377127A1/en active Granted
- 1978-01-10 PL PL1978203913A patent/PL120630B1/en unknown
- 1978-01-10 DE DE2800893A patent/DE2800893C2/en not_active Expired
-
1980
- 1980-10-01 JP JP55138199A patent/JPS5829634B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DK8878A (en) | 1978-07-11 |
| FI72410C (en) | 1987-05-11 |
| ZA7810B (en) | 1978-10-25 |
| AU3216678A (en) | 1979-07-12 |
| SE7800104L (en) | 1978-07-11 |
| FI72410B (en) | 1987-01-30 |
| FR2377127A1 (en) | 1978-08-04 |
| DE2800893C2 (en) | 1982-10-14 |
| JPS56142670A (en) | 1981-11-07 |
| NL7800272A (en) | 1978-07-12 |
| GB1579033A (en) | 1980-11-12 |
| DK149674C (en) | 1987-04-13 |
| JPS5829634B2 (en) | 1983-06-23 |
| FR2377127B1 (en) | 1982-04-30 |
| FI780012A (en) | 1978-07-11 |
| IT1089179B (en) | 1985-06-18 |
| PL203913A1 (en) | 1978-07-17 |
| AU511885B2 (en) | 1980-09-11 |
| SE437438B (en) | 1985-02-25 |
| JPS5387675A (en) | 1978-08-02 |
| NZ186177A (en) | 1981-03-16 |
| JPS5649460B2 (en) | 1981-11-21 |
| BE862760A (en) | 1978-05-02 |
| DE2800893A1 (en) | 1978-07-13 |
| DK149674B (en) | 1986-09-01 |
| PL120630B1 (en) | 1982-03-31 |
| ES465682A1 (en) | 1978-10-01 |
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