KR910006248B1 - Charge transfer device - Google Patents

Abstract

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Description

Charge transfer device

1 is a circuit diagram showing the main parts of one embodiment according to the present invention.

2 is a diagram showing a potential relationship for explaining the first embodiment.

3 is a characteristic curve diagram for explaining the first embodiment.

4 is a block diagram showing the overall configuration of the charge transfer element.

5 is a partial cross-sectional view of the charge transfer device.

6 shows a potential propile of the charge transfer device.

FIG. 7 is a circuit diagram showing a specific configuration of a boost circuit used in the charge transfer device shown in FIG.

8 is a timing chart of a control pulse used in the boosting circuit shown in FIG.

FIG. 9 is a circuit diagram showing a reference voltage generating circuit used in the boosting circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

10: voltage generating circuit 11: boosting circuit

12: deflection type MOS transistor 13: constant voltage source

14: constant current source 20: boost circuit

30: comparison control circuit 31, 32: level shift circuit

32: level shift circuit 33: comparator

48 input unit 49 charge transfer unit

50: floating diffusion region 51: output gate electrode

52 drain region 53 reset gate electrode

53: reset gate electrode 56: output circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a charge transfer device used in a solid state imaging device, a charge transfer type delay line, a comb filter, a transversal filter, and the like, in particular a drain region for discharging unnecessary charges. The present invention relates to a telephone transmission element having an improved portion for supplying a predetermined voltage.

One output method of an output circuit in a charge transfer device (hereinafter referred to as CTD) integrated on a semiconductor substrate is to use a floating diffusion region, and one of the CTDs employing this output method is output. In order to widen the dynamic range of the arc, that is, the dynamic range, a voltage boosted by the boost circuit is supplied to the drain region.

FIG. 4 is a block diagram showing the overall configuration of a CTD equipped with the boost circuit as described above, and FIG. 5 is a partial cross-sectional view of the CTD shown as a block diagram in FIG. 4 and 5, reference numeral 41 denotes an input terminal, 42 denotes an output terminal, and 43 denotes a first power terminal to which a power supply voltage (VDD) of the high potential side is supplied. Denotes a second power supply terminal supplied with a low-voltage power supply voltage (VSS; hereinafter referred to as a ground voltage), reference numeral 45 denotes a P-type semiconductor substrate and 46 denotes an N-type buried on the P-type semiconductor substrate 45 Channel region 47 is an insulating film, 48 is an input unit for converting the input analog signal into signal charge by applying a predetermined DC bias voltage to the analog signal input from the input terminal 41, and 49 is an input unit 48. Charge transfer unit for transferring the charge, 50 is this charge Floating diffusion region consisting of an N-type diffusion region and adjacent to the output gate electrode 51 positioned at the last end of the sending section 49, 52 is a drain region consisting of an N-type diffusion region to which a predetermined potential is applied. In addition, 53 is a reset gate electrode provided on the substrate between the floating diffusion region 50 and the drain region 52 through the insulating film 47, where the reset pulse? R is a high voltage VRL and a high voltage. The reset pulse? R which changes between the VRHs is supplied. Here, when the reset pulse øR is the high voltage VRH, the accumulated charge accumulated in the floating diffusion region 50 is discharged to the drain region 52 under the reset gate electrode 53. .

Reference numeral 54 denotes an enhancement type MOS transistor (hereinafter referred to as type E) for charge detection, in which a gate is connected to the floating diffusion region 50 and its drain is connected to a power supply voltage VDD. The source of the type MOS transistor 54 is connected to the output terminal 42. Reference numeral 55 denotes a circuit block having a current source function composed of at least one MOS transistor, the circuit block 55 having one end connected to the source of the charge detection MOS transistor 54 and the other end thereof being the ground potential. Connected to a VSS, the circuit block 55 and the MOS transistor 54 constitute a source follower output circuit 56 so that the signal charges output to the floating diffusion region 50 The signal is converted and output.

Meanwhile, as shown in FIG. 5, the charge transfer unit 49 is a two-phase drive type CTD driven through two phase transfer clocks ø1 and ø2, respectively, to determine the charge transfer direction. Two transfer electrodes 57i and 58i (i = l to n) each composed of a polysilicon layer per phase, each having an output gate electrode 51 to which a DC bias voltage VB is applied Equipped. Reference numeral 59 denotes a boosting circuit for boosting a predetermined voltage. The boosted voltage is applied to the drain region 52 as a reset voltage vgg, and the value of the voltage VGG is a normal power supply. It is set higher than the voltage VDD.

The operation of such a CTD will be described with reference to the potential profile shown in FIG. When the input unit 48 converts an analog input signal having an appropriate DC bias into positive signal charges corresponding to the input level, the signal charges are transmitted by the charge transfer unit 49, so that the floating diffusion region ( The accumulated charge q (shown in FIG. 6) is detected by the output circuit 56 at a predetermined moment, converted into a voltage signal, and then converted into a voltage signal by the output terminal 42. Is output. However, at this time, since the reset pulse øR is the low voltage VRL, the potential value PRL under the reset gate electrode 53 at this time maintains the drain level maintaining the level PD of the reset voltage VGG. It becomes a value which cuts off between the area | region 52 and the floating diffusion area | region 50. FIG.

Next, when the reset pulse øR becomes the high voltage VRH, the potential value PRH under the reset gate electrode 53 is formed between the floating diffusion region 50 and the drain region 52. As a result, the accumulated charge in the floating diffusion region 50 is discharged as unnecessary charge to the drain region 52 through the lower portion of the reset gate electrode 53, thereby allowing the floating diffusion region 50 to be discharged. ) Is reset to the value PD of the drain region 52 corresponding to the reset voltage VGG0.

However, the dynamic range DR of the output signal detected by the output circuit 56 and converted into a voltage signal has a potential value PD in the drain region 52 and a potential value PG under the output gate electrode 51. Difference (PD-PG), which is the lowest allowable voltage in relation to the potential value PnL below the final transfer electrode 58n. When set to the allowable value, the reset voltage VGG is higher than VDD, so the dynamic ranger DR of the output signal is quite large. In other words, even when the applied voltage VB is set to a value lower than VDD, and the boosted reset voltage VGG is set equal to the power supply voltage VDD, a somewhat large dynamic range DR can be obtained.

In addition, as described above, when the reset voltage VGG of the drain region 52 is higher than the power supply voltage VDD, the MOS transistor 54 in the output circuit 56 is reset at the time of reset of the floating diffusion region 50. A high reset voltage is applied to the gate. At the time of signal detection, the gate voltage of the transistor 54 is VG (VG? HVGG), the drain-source voltage VDS, the gate-source voltage VGS, the dark threshold voltage VTH, and the source voltage (output terminal 42). ) Is expressed as VO,

Become. Therefore, in order for the MOS transistor 54 to almost saturate at the time of signal detection,

Since it is necessary to be, by substituting the formulas (1) and (2) into this formula (3)

It becomes necessary to become. That is, in the case where a linearity is required to some extent as an output signal, it is necessary to define the threshold voltage relationship so that the expression (4) is almost satisfied at the time of signal detection.

)는 제8도의 타이밍챠트로 도시해 놓았는바, 즉 제7도에 있어서 참조부호61은 기준전압(VREF)을 출력시켜 주는 기준전압원, 62는 기 기준전압(61)에 일단이 접속된 E형 MOS트랜지스터, 63은 이 E형 MOS트랜지스터(62)의 다른단에 일단이 접속된 E형 MOS트랜지스터, 64는 상기 2개의 MOS트랜지스터(62,63)의 접속점에 일단이 접속된 용량이고, 상기 MOS트랜지스터(63)은 다른 단은 승압된 전압이 출력되게 되는 출력단자(65)로 되어 있다. 그리고, 상기 용랑(64)의 다른 단 및 MOS트랜지스터(63)의 게이트에는 제어펄스(

)가 인가되고, MOS트랜지스터(62)의 게이트에는 제어펄스(CP)가 잉가되게 되는바, 이에 따라 제어펄스(CP)가 ＂L＂레벨인 타이밍(t1)에서는 MOS트랜지스터(62)가 온되고 MOS트랜지스터(63)가 오프되어 용량(64)에는 MOS트랜지스터(62)를 통하여 기준전압원(61)의 기준전압(VREF)이 충전되게 된다. 다음에 제어펄스(DP)가 ＂H＂레벨인 타이밍(t2)에서는 MOS트랜지스터(62)가 오프되고, MOS프랜지스터(63)가 온되어 출력단자(65)의 전압은 기준전압(VREF)에 대해 제어펄스(CP)의 파고치(波高値)분만큼 승압된 것으로 되게 된다. 즉, 이 승압회로는 2체배(遞培)회로로 동작하게 된다. 또, 상기(4)식을 만족시키기 위해서는 승압회로로서 3체배이상의 구성인 것을 이용하게 될 필요도 있게 된다.FIG. 7 is a circuit diagram showing a specific configuration of the boosting circuit 59 used in the CTD, and the control pulses CP,

) Is shown as a timing chart of FIG. 8. That is, in FIG. 7, reference numeral 61 denotes a reference voltage source for outputting a reference voltage VREF, and 62 denotes an E type having one end connected to the reference voltage 61. MOS transistor, 63 is an E-type MOS transistor whose one end is connected to the other end of the E-type MOS transistor 62, 64 is a capacitance whose one end is connected to the connection point of the two MOS transistors 62 and 63, and the MOS transistor The transistor 63 has an output terminal 65 for outputting a boosted voltage at the other stage. In addition, a control pulse (

) Is applied to the gate of the MOS transistor 62, so that the control pulse CP is excessive. Accordingly, the MOS transistor 62 is turned on at the timing t1 at which the control pulse CP is at the L level. The MOS transistor 63 is turned off so that the capacitor 64 is charged with the reference voltage VREF of the reference voltage source 61 through the MOS transistor 62. Next, at the timing t2 at which the control pulse DP is at the HH level, the MOS transistor 62 is turned off, and the MOS transistor 63 is turned on so that the voltage at the output terminal 65 reaches the reference voltage VREF. The pressure is increased by the crest value of the control pulse CP. In other words, this boosting circuit operates as a multiplication circuit. In addition, in order to satisfy the above expression (4), it is necessary to use a configuration of three or more times as a boosting circuit.

By the way, the reference voltage source 61 used in the above-mentioned synapse circuit 59 is normally used as the power supply voltage (VDD), or the reference voltage generation circuit by a combination of (MOS) transistor, that is, Conventionally, as the reference voltage generating circuit, one having a configuration as shown in FIG. 9 has been used.

In this circuit, two deflation type (hereinafter referred to as D type) MOS transistors 66 and 67 are connected in series between an application point of the power supply voltage VDD and an application point of the ground voltage VSS. The gate of is connected to each of its drains, and the reference voltage VREF is output from the series connection point of both transistors 66 and 67.

In addition, the D-type MOS transistors 66 and 67 constituting the reference voltage generating circuit shown in FIG. 9 have the reset gate electrode 53, the floating diffusion region 50, and the drain region 52. Since the same conductivity type and the same D type as that of the MOS transistor structure constituted by the MOS transistor structure, each threshold voltage VTHD becomes a negative value, while the MOS transistor 54 constituting the output circuit 56 is provided. ) Is of type E, the threshold voltage VTHE becomes a positive value.

For this reason, if the reference voltage generating circuit shown in FIG. 9 is used as the reference voltage source 61 of the boosting circuit shown in FIG. 7, the following unreasonable points arise. In other words, when the dynamic range DR of the CTD output signal is set to be wide, it is good to increase the boost voltage of the boost circuit 59 so that the potential PD formed under the drain region 52 becomes high. When the bias voltage VFD of the signal in the region 50 exceeds the voltage VDD + VTHE, which is the sum of the power supply voltage VDD and the threshold voltage VTHE of the transistor 54, the transistor 54 desaturates. Entering the area, the linearity of the output signal is lost. Therefore, the upper limit of the boost voltage in the boost circuit 59 coincides with the maximum value that can maintain the linearity.

)로 된다. 또, 프로세스관리상의 상한에 의해 VTHD와 VTHE의 값은 독립적으로 변동하지만, 제9도에 도시된 기준전압발생회로는 동일도전형의 MOS트랜지스터로 구성되어 있으므로 프로세스에 의한 기준전압의 변동은 미미하게 된다. 따라서, 제7도에 도시된 승압회로에서는 승압전압(VGG)의 값이 프로세스의 관계없이 일정하게 되고, 상기(5)식으로부터 바이어스전압(VFD)의 동작범위를 프로세스변동의 영향을 받게 된다. 즉, |VTHD| 가 클때에는 하한(下限)의 마진(margin)이 적게 되고, VTHE가 작을 경우에는 상한(上限)의 마진잉적은 상태로 되게 된다. 따라서 |VTHD| 가 클때에는 다이내믹레인지(DR)가 작게 되고, VTHE가 작을 때 에는 출력회로(56)를 구성하는 MOS트랜지스터(54)를 포화동작시키기 위해 승압전압(VGG)을 낮게 설정할 필요가 있기 때문에 결과적으로 역시 다이내믹레인지(DR)가 작아지게된다.Where VTHE =

). In addition, although the values of VTHD and VTHE fluctuate independently due to the upper limit of process management, the reference voltage generating circuit shown in FIG. 9 is composed of MOS transistors of the same conductivity type, so the variation of the reference voltage by the process is insignificant. do. Therefore, in the boost circuit shown in FIG. 7, the value of the boost voltage VGG is constant regardless of the process, and the operating range of the bias voltage VFD is affected by the process variation from the above expression (5). That is, | VTHD | When is large, the margin of the lower limit becomes small, and when the VTHE is small, the margin of the upper limit becomes low. Thus | VTHD | The dynamic range DR becomes small when is large, and when the VTHE is small, the boost voltage VGG needs to be set low to saturate the MOS transistor 54 constituting the output circuit 56. The dynamic range DR becomes small.

As described above, in the conventional output circuit, the maximum amplitude range margin of the signal in the floating diffusion region necessary for maintaining the linearity of the signal of the output signal is affected by the variation of the process, in particular, the threshold voltage of the depleted linear MOS transistor. There is a problem of being written down.

Accordingly, the present invention has been made in consideration of the above-described circumstances. Even in the case of a certain amount of flow fluctuation, the signal in the floating diffusion region can increase the maximum amplitude range margin, and the linearity and S / N ratio under a predetermined power supply voltage are increased. It is an object of the present invention to provide a charge transfer device capable of obtaining a good output signal with a wide dynamic range.

The present invention for realizing the above object is a floating diffusion region which is formed on the semiconductor substrate and the signal charges from the charge transfer unit are transferred, and a drain region, reset which discharges unnecessary charges by applying a reset voltage. A reset gate electrode for controlling the discharge of accumulated charge accumulated in the floating diffusion region to the drain region in response to a pulse, and the reset gate electrode when discharging the accumulated charge accumulated in the floating diffusion region to the drain region. Voltage generating means for generating a voltage corresponding to a potential lower by a predetermined value α than a potential to be formed below; boosting means for boosting a predetermined voltage and supplying the boosted voltage as a reset voltage to the drain region; Generate an error voltage depending on a difference between the output voltage of the output voltage and the voltage boosted by the voltage boosting means. And the comparison control means for controlling the step-up operation in the step-up means based on this error voltage.

In the charge transfer device according to the present invention composed of the above means, the value of the boosted voltage from the boosted voltage supplied as a reset voltage to the drain region is controlled in accordance with the process variation, in particular the variation of the threshold voltage of the depoly-linear MOS transistor. As a result, the interworkability of the reset voltage with respect to the process variation is good, the output dynamic range is always kept constant, and the output signal with good linearity and S / N ratio can be obtained.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In the charge transfer device CTD according to the present invention, a circuit having the configuration as shown in FIG. 1 is used in place of the boost circuit 59 in FIG. 4, and in FIG. A voltage generation circuit that equally detects a potential under the set gate electrode 53 and generates a voltage corresponding to a potential lower by an α value than the detected potential, and 20 boosts a predetermined voltage to boost the boosted voltage. A boosting circuit for supplying the drain region 52 as the reset voltage VGG, and 30 corresponds to a difference between the voltage generated by the voltage generating circuit 10 and the boosting voltage from the boosting circuit 20. The comparison voltage is generated as an error voltage and controls the boosting operation of the boosting circuit 20 in accordance with the error voltage.

On the other hand, the voltage generation circuit 10 includes a boost circuit 11 for generating a constant voltage, a D-type MOS transistor 12 and a constant voltage source 13 having the same structure as the reset gate electrode 53 of FIG. And a constant current source 14, wherein the booster circuit 11 generates a constant voltage at a voltage slightly higher than the potential value formed under the channel of the MOS transistor 120. The constant voltage generated by 11 is supplied to the drain of the transistor 12. The high voltage VRH of the reset pulse? R supplied to the reset gate electrode 53 is supplied to the gate of the transistor 12. The constant voltage source 13 having the same value as that is connected, so that the transistor 12 is always in a conductive state, and the constant current source 14 is connected to a source of the transistor 12, and the source and the constant current are connected. The voltage generated at the connection point with the circle 14 is It is to be supplied to the bridge control circuit 30.

In addition, the comparison control circuit 30 level-shifts the voltage generated by the voltage generation circuit 10 and the voltage-shifting circuit 31 to level-shift the voltage generated by the voltage generation circuit 10. A level shift circuit 32 for shifting, and a comparator 33 for outputting an error voltage corresponding to the output voltage difference from the level shift circuits 31 and 32, wherein the output error from the comparator 33 The voltage is supplied to the booster circuit 20 as a control input. At this time, the booster circuit 20 boosts the voltage by changing the reference voltage VREF of FIG. 7 based on the control input.

Next, the operation of the circuit having the above-described configuration will be described using the potential profile shown in FIG.

In the voltage generation circuit 10, since a constant voltage is applied from the boost circuit 11 to the drain region 15 of the MOS transistor 12, a constant potential PD is generated at the lower portion thereof. In addition, since the constant voltage VRH from the constant voltage source 13 is applied to the gate of the MOS transistor 12, the potential PRH is below the same as in the case of the reset gate electrode 53 shown in FIG. Will occur.

On the other hand, since the constant current source 14 is connected to the source region 16 of the transistor 12 and the flow current IO flows through the constant current source 14 between the drain and the source region, the source region of the transistor 12. The electric potential of (16) is set to the electric potential PRH at the lower part of the channel region minus the lowering amount α of the electric potential value by the current IO (PRH-α), and the voltage corresponding to this value is the source region 16. Will be generated. Note that the value corresponding to α is at the time of reset which is the difference between the high level potential PRH formed under the reset gate electrode 53 and the potential PD of the drain region 52 in FIG. The current value IO is adjusted to be equal to the margin. This voltage generating circuit 10 is adjusted. Since the voltages from the voltage generating circuit 20 and the boosting circuit 20 are higher than the power supply voltages used in the boosting circuit 20 and the comparison storage circuit 30, both voltages are level shift circuits 3,35. After the level shift at, it is supplied to the comparator 33, and the comparator 33 outputs a voltage corresponding to the difference between the two voltages. In addition, the boosting operation of the boosting circuit 20 is controlled according to the error voltage output from the comparator 33. When the output of the level shift circuits 31 and 32 is matched, The boosted voltage VGG becomes stable.

Therefore, if the potential PG under the output gate electrode 51 and the potential value PnL under the last stage transfer electrode 58n are set to be almost the same value, the dynamic range DR may be changed even though the process varies. Is the value, that is, the threshold voltage of the D-type MOS transistor | VTHD | Even if this fluctuates, it can be maintained at a constant value.

As described above, according to the above embodiment, the reset voltage boosted to the drain region 52 is applied to set the dimix range of the output wide. You get a signal. Further, according to the above embodiment, the potential value under the reset gate electrode 53 is equivalently detected, and the process variation according to the detected potential value, in particular, the threshold voltage | VTHD | By interlocking the reset voltage (VGG) with respect to the variation of, it is possible to substantially keep the output dynamic range (DR) constant.

3 is a characteristic curve showing the change in dynamic range DR with respect to the variation in the threshold voltage (| VTHD |) accompanying the process variation, in which the curve (a) is from the above embodiment, and the curve ( b) shows the conventional thing which fixed VGG.

As can be seen from the figure, in the conventional curve (b), | VTHD | Because the dynamic range (DR) fluctuates significantly within the range of process variation of the | VTHD | At high, the dynamic range DR becomes insufficient.

In contrast, in the curve (a) according to the embodiment according to the present invention, the dynamic range DR is kept substantially constant within the range of the process variation width.

On the other hand, in the conventional curve (b), | VTHD | The dynamic range DR becomes constant at the lower part of the curve, which corresponds to the case where PRH < PD in FIG. 6 is generally known. In this state, it is known that the noise component increases, so | VTHD | Using in the lower part is not a good idea.

In addition, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the voltage generating circuit 10 has an α as much as the potential PRH under the reset gate electrode 53. Although the use of the constant current source 14 in the case of generating a voltage corresponding to the low potential PRH-α has been described, this actually returns the value of the constant voltage source 13 applied to the gate of the MOS transistor 12. It may be set to a value lower than the high voltage VRH of the reset pulse? R applied to the set gate electrode 53, and may also be executed by adjusting the channel width W of the MOS transistor 12.

Further, the boost circuit 20 is configured to control the boost operation by the error voltage from the comparison control circuit 30. However, the present invention is not limited thereto, and for example, the reference voltage VREF is always constant. In this case, the voltage boosting output may be varied by changing the pulse width of the control pulse CP according to the error voltage from the comparison circuit 30.

As described above, according to the present invention, even if there is a certain process variation, the maximum amplitude range margin of the signal in the floating diffusion region can be increased, and linearity and S / N ratio are excellent under a predetermined power supply voltage. It is possible to provide a charge transfer device capable of obtaining a wide output signal with a dynamic range.

Claims (2)

A floating diffusion region 50 which is formed on the semiconductor substrate 45 and in which signal charges from the charge transfer unit 49 are transferred, and a drain region 52 that discharges unnecessary charge by applying a reset voltage. A reset gate electrode 53 for controlling discharge of the accumulated charge of the floating diffusion region 50 to the drain region 52 according to a reset pulse, and draining the stored charge of the floating diffusion region 50 with the drain pulse. In the case of discharging to the region 52, the voltage generating means 10 for generating a voltage corresponding to a potential lower than the potential formed under the reset gate electrode 53 by a predetermined value α, Step-up means 20 for supplying the step-up voltage as the reset voltage to the drain region 52 generates an error voltage corresponding to the difference between the output voltage from the voltage generation means 10 and the step-up voltage. Error A charge transfer device, characterized in that it is configured by having a comparison control means 30 which controls the step-up operation in the step-up means 20 is based on. 2. The potential of the predetermined potential value? Is formed under the reset gate electrode 53 when the accumulated charge of the floating diffusion region 50 is discharged to the drain region 52. A charge transfer element, characterized in that it is set to a value corresponding to a difference from the potential of the drain region (52).

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