JPS5780773A - Charge coupled device and driving method therefor - Google Patents

Charge coupled device and driving method therefor

Info

Publication number
JPS5780773A
JPS5780773A JP15651280A JP15651280A JPS5780773A JP S5780773 A JPS5780773 A JP S5780773A JP 15651280 A JP15651280 A JP 15651280A JP 15651280 A JP15651280 A JP 15651280A JP S5780773 A JPS5780773 A JP S5780773A
Authority
JP
Japan
Prior art keywords
gate
pulse
sampling
phis1
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15651280A
Other languages
Japanese (ja)
Other versions
JPH0132671B2 (en
Inventor
Hiroo Wakaumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15651280A priority Critical patent/JPS5780773A/en
Publication of JPS5780773A publication Critical patent/JPS5780773A/en
Publication of JPH0132671B2 publication Critical patent/JPH0132671B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To perform alternate sampling in displaced phase of 180 deg. between a main unit and a sub unit by supplying a pulse synchronized with the pulse width of a master clock to a sampling gate provided adjacent to a bias gate. CONSTITUTION:In a main unit, a preset pulse ID1 become ON during the OFF period of a pulse applied to a sampling gate phiS1, and charge is charged under a bias gate G1. When the pulse ID1 alters to OFF, the charge under G2 gate is discharged to the input diode 13 side through the bias gate G1. When the pulse to the gate phiS1 becomes ON at the time t4, the charge under the G2 gate is transferred to the transfer channel gate phi1. When the gate phiS1 becomes OFF at the time t4, this carrier flow is interrupted. The sequential samplings are carried out in this cycle, and the sampling pulse is equalized to the width of the master clock. The operation of the sub unit is similarly operated with the phase phiS2 of the sampling pulse of 180 deg. difference.
JP15651280A 1980-11-07 1980-11-07 Charge coupled device and driving method therefor Granted JPS5780773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15651280A JPS5780773A (en) 1980-11-07 1980-11-07 Charge coupled device and driving method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15651280A JPS5780773A (en) 1980-11-07 1980-11-07 Charge coupled device and driving method therefor

Publications (2)

Publication Number Publication Date
JPS5780773A true JPS5780773A (en) 1982-05-20
JPH0132671B2 JPH0132671B2 (en) 1989-07-10

Family

ID=15629386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15651280A Granted JPS5780773A (en) 1980-11-07 1980-11-07 Charge coupled device and driving method therefor

Country Status (1)

Country Link
JP (1) JPS5780773A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017940A (en) * 1973-06-13 1975-02-25
JPS53136976A (en) * 1977-05-06 1978-11-29 Nec Corp Charge coupling device and its driving method
JPS5427780A (en) * 1977-08-02 1979-03-02 Rca Corp Charge coupled device gain control system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017940A (en) * 1973-06-13 1975-02-25
JPS53136976A (en) * 1977-05-06 1978-11-29 Nec Corp Charge coupling device and its driving method
JPS5427780A (en) * 1977-08-02 1979-03-02 Rca Corp Charge coupled device gain control system

Also Published As

Publication number Publication date
JPH0132671B2 (en) 1989-07-10

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