GB2169445A - Input circuit for charge-coupled devices - Google Patents

Abstract

An input circuit for a charge coupled device makes use of the "fill-and-spill" principle. As shown a diode or source 17 supplies electrons to a succession of zones each having an associated electrode, the electrodes comprising a transfer electrode 18, a storage electrode 19, an afflux electrode 20, a depletion electrode 21, a signal electrode 22 and a control electrode 23. The storage electrode and the control electrode are connected to the same input pulse voltage. The depletion zone is separated from the signal zone by a second diode which is connected to the first diode. <IMAGE>

Description

SPECIFICATION Input circuit for charge-coupled devices The subject of the invention is a novel concept of input circuit for charge-coupled devices (CCD's). Components of this type are widely used in micro-electronics and optoelectronics. both in the form of individual rows and also as rows grouped together to form planar arrangements.

Where charge-coupled devices (CCD's) are concerned, two types of input circuits are known. On the one hand, the so-called electrical signal inputs and on the other reference charge generators. A typical example of the first group is the input circuit which operates on the ''fill and spill" method. With this, there is adjacent to the first electrode of a CCD shift register a diode zone. A direct current voltage is applied to this first electrode. The second electrode is the actual input electrode.

To this is applied the electrical signal in respect of which proportional charge packets are to be generated which are then shifted in the same rhythm as the clock frequency from cell to cell in subsequent CCD registers, the third, fourth and all other electrodes are already register electrodes. For operation, a pulse voltage is applied to the input diode zone. its frequency being equal to the clock frequency. shifting the diode zone from a sufficiently high inhibiting level for in each case a short period of time to a clearly defined lower inhibiting voltage.For only a "short period of time" because after the "filling" of the potential well under the second electrode (the input electrode), which takes place during the low inhibiting voltage, there must be sufficient time for "spilling" of the excess charge out of the potential well under the second electrode over the potential barrier under the first electrode into the input diode zone, before the charge is taken over from the first potential well into the successive register cell. This spilling can only take place if the input diode zone is at the sufficiently high inhibiting level.

A typical representative of the second group is a so-called white value generator, such as is used with optical CCD sensor rows (e.g.

CCD 133 by Fairchild and L 133 by VEB WF).

The white value generator is controlled by that pulse which triggers the transfer of the optically generated signal charges from the sensors into the CCD shift register. This pulse is present at the electrodes of the white value generator while the diode zone which is in turn adjacent the first electrode is kept at a constant direct current voltage level.

Usuazlly, a CCD register is only provided with one input circuit of one of the two groups. In DD Fat. Application WP H 01 L/2 53669/1, a complex input circuit is proposed with which it is possible to carry out both an electrical signal input and also a generation of white signals. Thus, it is possible simultane ously to process electrical and optical signals.

For the functioning of the electrical signal input, thereby the above explained special pulse voltage is required at the input diode zone, whereas as white value generation takes place through the aforesaid transfer pulse.

In the case of the known white value generators, only the duration of one clock flank of the transfer pulse is available for the "spilling" of excess charge. Thus, with very steep pulses, the magnitude of the generation reference charge is not all too accurately determined.

The object of the invention was to eliminate the defects inherent in the state of the art.

The invention was based on the problem of constructing an input circuit for charge-coupled devices which can be used both for electrical signal input and also for the generation of reference charges, which requires no special pulse voltage and which generates reference charges of great accuracy.

In order to resolve this problem, an input circuit is designed which carries into effect a novel concept of charge input. Furthermore, in this circuit there is a spatial separation of the zones which serve for "filling" a potential well with charge from zones which are intended to "spilling" excess charge.

The substance of the invention is explained on the assumption that the CCD shift register is a two-phase register (or four-phase register) in which the clock pulse sequence is applied to one phase while the other phase is maintained at a direct current voltage level. Thus, the working mode of a single-phase register is covered at the same time. If the thoughts underlying the invention are to be used for a three-phase register as well as for a twophase register (or four-phase register) in which there are clock pulse sequences at both phases, then for the control voltages of the individual electrodes of the input circuit there are certain level shifts which need not be explained in greater detail to a man skilled in the art.

According to the invention, the input circuit is designed as follows: At the start of the CCD shift register separated only by a control electrode with the underlying control zone from this latter, there is a signal zone which is preferably monitored by a signal electrode in which a potential well forms. The depth of this well, when a signal electrode is provided, is proportional to the voltage present at it. Between the signal zone and a diode zone is a depletion zone which can be monitored by a depletion electrode, which occupies about the same width as the signal zone (the term width is taken to mean the geometrical measurement at a right-angle to the direction of feed of the CCD register).

Perpendicular to the direction of feed of the CCD register the signal zone is adjacent to an afflux zone which can be monitored by an afflux electrode, adjacent to which there is in turn a collecting zone with a collecting electrode above it. This latter is separated from a diode zone by a transfer zone with a transfer electrode above it, this diode zone preferably being electrically connected to that which borders on the depletion zone. If the aforesaid electrodes are classified by the terms normally used with two-phase CCD's, then the signal and gathering electrodes must be included among the storage electrodes, i.e. under them potential wells form in which charges can be stored.The depletion, afflux, transfer and control electrodes are therefore transfer electrodes, i.e. under them potential barriers form opposite the storage zones, i.e. the signal charges only pass through these zones during transfer from one storage zone to the other or in the event of transfer between diode zones and storage zones. The first CCD register electrode adjacent the control electrode is a storage electrode at which the clock pulse sequence is present.

Electrical signal input is, according to the invention, achieved as follows: The transfer, storage and control electrodes are supplied with the clock pulse sequence needed for the CCD register. if the afflux zone is being monitored by an electrode, then this afflux electrode is supplied by a direct current voltage, preferably being for the purpose connected to the second phase of the CCD register which is at a direct current voltage level.

The two diode zones which are preferably connected to each other are polarzied in the inhibiting direction with a direct current voltage of adequate magnitude, in respect of which explanations will be given hereinafter. In the normal way, the electrical input signal is applied to the signal electrode. If the depletion area is being monitored by an electrode, then this depletion electrode is maintained at a direct current voltage leve, for which preferably the direct current voltage which controls the second phase of the CCD register is used.

Operation is however also possible with interchanged feeds for these two electrodes, i.e.

the input signal is applied to the depletion electrode while the signal electrode is supplied with the aforesaid direct current voltage.

The inhibiting voltage at the diode zone adjacent the transfer electrode is chosen to be sufficiently high that at the high level of the clock pulse sequence the potential barrier under the transfer electrode is lowered sufficiently that charges (with regard to substrate they are minority carriers) can flow unimpeded into the potential well under the storage electrode. The potential level in the diode zone must however in any event be lower than the extreme value of the potential in the afflux zone which is completely depleted of minority carriers so that during the high level, the charge carriers originating from the diode zone can only flow into the well under the storage electrode.

During the subsequent low level of the clock pulse sequence, the potential under transfer and storage electrodes is raised, in fact sufficiently that the potential well under the storage electrode is still shallower than the low point of the potential in the afflux zone even when the zone is completely depleted of minority charge carriers. Therefore, during the low level, all minority charge carriers flow out of the potential well under the storage electrode through the afflux zone into the potential well under the signal electrode. Under the control electrode which is likewise at low level, there is a potential barrier so that charge transfer into the next CCD register in succession is prevented. The potential barrier of the depletion zone is substantially smaller than that of the control zone.All excess charge carriers out of the signal zone flow over the barrier of the depletion zone into the adjacent diode zone until the potential in the signal zone reaches the barrier value in the depletion zone. In proportion to the value of the electrical signal applied to the signal electrode, so there remains in the signal zone a charge packet which, at the subsequent high level of the clock pulse sequence, can flow into the CCD register. Then the clock voltage is supplied to the control electrode and the first CCD register storage electrode. Thus, the potential barrier under the control electrode is dissipated and the charge carriers can without hindrance flow from the signal zone (under the signal electrode) into the potential well under the first CCD register storage electrode.During this high level, once again charge carriers flow out of the diode zone over the transfer zone monitored by the transfer electrode and into the potential well under the storage electrode and the entire process of charge input which has been described thus far is repeated.

By reason of the fact that the depletion zone, due to the construction according to the invention, is about the same width as the signal zone, it is ensured that the potential in the signal zone reaches the value established by the potential barrier of the depletion zone by reason of spilling of the excess charge carriers. The magnitude of the charge packets remaining in the signal zone and subsequently flowing into the CCD register can thus be precisely defined by the voltage applied at the signal electrode. Furthermore, attention should be drawn to the fact that in the operating mode according to the invention and as described, the duration of an entire low or high phase of the clock pulse is available for filling and/or spilling. With the known fill and spill method, filling and spilling must take place during the low phase time only, which impairs accuracy of charge input in comparison with the method according to the invention, particularly at high clock frequencies.

A particular advantage of the method according to the invention is the fact that no special pulse voltage is required for the input circuit. The suggested input circuit uses the impulse voltage prepared for the CCD register, the input diodes are at a direct current voltage.

Using the input part for input of a reference charge (for example a "white value") in the case of optical CCD sensor rows, will according to the invention take place as follows: The transfer, storage and control electrodes are fed with the transfer pulses needed for charge transport between sensor cell and CCD register. The other electrodes are supplied in exactly the same way as in the case of electrical signal input. The voltage value present at the signal electrode determines the magnitude of the reference charge. The transfer pulse sequence consists of short high phases which occur during the high phase of a clock pulse, are shorter than or equal in their duration to the high phase of a clock pulse. During the entire light integration phase of the sensor row, the low level of the transfer pulses persists.

Generation of the reference charge occurs in principle in exactly the same way as described above for electrical signal input, except for the fact that the charge packet generated as the result of a transfer pulse is not right away passed into the CCD register but is stored in the signal zone beyond the light integration phase and thus low level phase of the transfer pulse sequence and is only passed into the CCD register at the next transfer pulse in succession.

The reference charge does not change its value thereby, since all the extra charge carriers added, such as for example the thermally generated, are being constantly depleted flowing through the depletion zone into the input diode.

As explained, the input arrangement according to the invention can, by appropriate switchover of the supply for transfer, storage and control electrode, be used either for electrical signal input or for reference charge recovery.

In a special embodiment of the invention, simultaneous electrical signal input and reference charge recovery are possible. In this case, in addition to the input arrangement so far described, another similar arrangement is used. The arrangement previously described and positioned in front of the first CCD register electrode in this case preferably serves for electrical signal input. The additional arrangement is set laterally against the CCD register, is used preferably for reference charge recovery and need not necessarily transfer the generated charge into the first CCD register storage electrode.According to the actual design of the embodiment, so the generated charge can pass into the second, third or other positioned storage electrode of the CCD register. "Lateral" disposition means that depletion, signal and control zones which in the above-mentioned basic arrangement were in the extended "axis" of the CCD register, are now located together with the other zones of the input circuit at a right-angle to and away from the "axis". This arrangement means that the depletion zone cannot now be any longer as wide as in the basic arrangement. In the case of reference level recovery with the transfer pulse (white value generation), the spilling of excess charge takes quite a time, namely the duration of the entire light integration phase.Thus, despite the narrower depletion zone, a high accuracy of the reference level (white value) is assured.

The lateral arrangement can be repeated. In the case of a white reference, it is recommended to shift two white values through the CCD register one after the other. In this case, the first white value, by virtue of transfer losses, may be reduced in height at the end of the register while the second reaches the row output in almost unmodified state and is thus an actual reference level.

For further details of the additional laterally disposed reference level arrangement, attention is drawn to the corresponding embodiment.

The invention will be explained in greater detail hereinafter with reference to an example of embodiment shown in the accompanying drawings, in which: Fig. 1 is a diagrammatic view of the input circuit according to the invention; Fig. 2a is a cross-section taken on the line AA' in Fig.1; Fig. 2b, c show potential diagrams; Fig. 3a is a cross-section taken along the line BB' in Fig. 1; Fig. 3b, c show potential diagrams; Fig. 4 is a layout drawing of a practical embodiment of the input circuit shown in Figs.

1 to 3, and Fig. 5 is a layout drawing of an embodiment of input circuit for two-fold reference level input.

The invention can be applied to both surface CCD's and also to buried channel CCD's.

In the embodiment, the basis adopted is a two-phase BCCD with a p-conductive substrate. Of course, the invention can also be carried into effect with n-conductive substrates.

Fig. 1 is a diagram showing the construction of the input circuit according to the invention.

In this, the potentials in all the zones are monitored by electrodes disposed above them.

The reference numerals used denote: 18 transfer electrode, 19 storage electrode, 20 afflux electrode, 21 depletion electrode, 22 signal electrode, 23 control electrode, 24 first BCCD register storage electrode, 25 transfer electrode for the second register cell, 26 sto rage electrode for the second register cell, 27 and 28 transfer and storage electrode for the third register cell, 29 and 30 transfer and storage electrode for the fourth register cell, 31 transfer electrode for the fifth register cell.

The diodes adjacent the transfer electrode 18 and the depletion electrode 21 are identified as a common zone 17 which is supplied with direct current voltage U, through the conductor 10. The electrodes 24, 27, 28 and 31 are supplied through clock pulse line 13 with clock pulse sequence U3. Electrodes 25, 26, 29 and 30 are connected to the direct current voltage U4 through direct current voltage conductor 14. The afflux electrode 20 is supplied with direct current voltage U6 and the depletion electrode 21 with direct current voltage U7. Preferably, the direct current voltage U4 needed for the BCCD register is used for U6 and U7. The voltage supplied to the signal electrode 22 through the conductor 11 determines the mangitude of the charge packet produced.The transfer, storage and control electrode (18, 19 and 23) are supplied with input pulse voltage U2 via input pulse voltage conductor 12. For U2, in the case of electrical signal input, the clock pulse sequence U3 is adopted while for a reference level recovery for optical sensor rows (white value generation), the transfer pulse sequence is used as u2 Fig. 2a shows a vertical section taken on the line AA'. In Figs. 2b and 2c are shown the potential patterns for the decisive stages of generation of the charge packet under the signal electrode 22. The buried channel storage zones are identified by reference numeral 15, the potential barrier generating dopings by 16 while the substrate is 32, the gate isolator 33 and the field isolater 34.

The n zone 17 is maintained at the inhibiting potential 36 (Fig. 2b). In the channel stopper zone 38 under the field isolator 34, the potential attains the substrate value 35. If the high level of U2 is present at the electrodes 18 and 19, then electrons flow out of the n zone 17 in the direction of the arrow 42 into the potential well 46 under the storage electrode 19 until the potential under the electrodes 18 and 19 reaches the value 36. In the zone which is completely depleted of electrons and which is under the transfer electrode 18, the potential will reach the value 37.

During the subsequent low level of U2 (Fig.

2c), the charge under the storage electrode 19 flows in the direction of the arrow 44 over the potential barrier 39 which is maintained under the afflux electrode 20, into the potential well 40 under the signal electrode 22.

Since the well 46 (Fig. 2b) was at first "overfilled" with electrons, then according to the steepness of the high-low pulse flank, so a small part of the charge will flow back in the direction of the arrow 43 and into the n zone 17. In the zones which are finally completely depleted of electrons and which are under the electrodes 18 and 19, the potential assumes the pattern 48 and 49. The capacity of the potential well 40 is determined by its relative depth with regard to the potential barrier 41 under the depletion electrode 21. All excess electrons flow in the direction of the arrow 45 into the n+ zone 17 until the potential under the signal electrode 22 reaches the barrier value 41.

Fig. 3a shows a vertical section taken on the line BB'. In Figs. 3b and 3c are shown the potential patterns for the decisive stages during input into the BCCD register of the charge packet located under the signal electrode 22.

Fig. 3b corresponds to the same actual point in time for which Fig. 2c was drawn. Under the control electrode 23, the potential barrier 48 has built up because the pulse voltage U2 has just assumed its low level. Were the input circuit to be used for electrical signal input, then U2 would equal U3 and under the electrodes 24, 27 and 28 (with complete depletion of electrons), there would be the potential patterns 50, 52 and once again 50.

Under the electrodes supplied with direct current voltage U4 and with complete depletion of electrons in the transfer zone there would be the potential 39 while in the storage zone there would be the potential 51. For the case of white value generation, Fig. 3b shows a moment during the light integration phase in which the clock pulse sequence U3 is attaining the low level. For U2, which would be the transfer pulse sequence with white value generation, then low level prevails over the entire light integration phase. Under the signal electrode 22, the potential alters to the value 47 as a result of the stored charge.

Fig. 3c shows the moment when the pulse voltage U2 assumes the high level. Both with electrical signal input and also with reference level recovery, the high phases at U2 and U3 drop at the same time. For the case of depletion of electrons, the potentials 53 and 54 evolve under the electrodes 27 and 28. The charge located under the signal electrode 22 flows in the direction of the arrow 56 over the lowered barrier 37 into the well 54 so that the potential under the first BCCD register storage electrode 24 rises to the value 55.

Simultaneously with the process shown in Fig.

3c, once again electrons flow out of the n' zone 17 and into the potential well 46 (see Fig. 2b) and the entire process as described is repeated.

Fig. 4 shows the layout of the most important levels of a practical embodiment of input circuit according to Figs. 1, 2 and 3. The storage electrodes 24, 26 and 28 of the BCCD register measure 10 X 30,um2. The individual lines mean: 60 boundary between field isolator (plus channel stopper zone) and gate isolator, 61 electrodes of the first electrode level (e.g. first poly-Si layer), 62 electrodes of the second electrode level (e.g. second poly-Si layer), 63 guide path level (e.g. Al), 64 contact window. The afflux electrode 20 and the depletion electrode 21 are in Fig. 4 connected directly to the electrode 25 and are thus connected to the direct current voltage U4. Operation of the circuit shown in Fig. 4 is covered by what has been stated with reference to Figs. 1, 2 and 3.

Fig. 5 shows the layout of the most important levels of an embodiment of input circuiC which is disposed laterally of the CCD register and which is preferably used for reference level recovery. Fig. 5 shows a detail from the initial part of a typical BCCD sensor row. The transport directions of the two BCCD registers, indicated at top and bottom in Fig. 5, are symbolized by the arrows 80 and 81. The transfer electrodes 69, 73 and 77, like the storage electrodes 70, 74 and 78, are supplied by the clock pulse sequence U3. The transfer electrodes 71 and 75 and also the storage electrodes 72 and 76 are fed by the direct current voltage U4. Similarly connected to U4 are the afflux, depletion and signal electrodes 20, 21 and 22.

Two white values are fed one after the other into each of the two BCCD registers while the transfer pulse sequence is taken as U,. As Fig. 5 shows, the depletion electrode 21 cannot any longer be made as wide as is possible with the basic embodiment in Fig. 1.

Since the low level phase of the transfer pulse and thus the depletion time for spilling of excess charge is very long, namely the duration of the entire light integration phase, the white values are generated with great accuracy.

The pulse voltage U2 is fed through the contact windows 82 and 84 to the electrodes 18 and 19 while the n zone 17 receives the direct current voltage Ul through the contact window 82.

The corresponding Al paths are not shown in Fig. 5 for the sake of greater clarity of illustration. The corner of the channel stopper zone identified by reference numeral 86 projects under the signal electrode 22 so that upon displacements of the planes in respect of one another for reasons of adjustment and preparation tolerances, a variation in the effective signal electrode area is compensated by the channel stopper zone 85 which likewise projects under the electrode 22.

Otherwise, Fig. 5 shows the same reference numerals as in Figs. 1 to 4. With regard to the functioning of the arrangement shown in Fig. 5, the description given with reference to Figs. 1 to 3 applies.

Claims (5)

1. Input circuit for charge-coupled devices, characterized in that adjacent to a first diode zone polarized in the inhibiting direction there are in succession a transfer zone, a storage zone, an afflux zone and a signal zone and in that adjacent to this signal zone are two further zones, namely a depletion zone and a control zone, the depletion zone separating the signal zone from a second diode zone polarized in the inhibiting direction and in that downstream of the control zone there is a CCD shift register which in turn starts with a storage zone and in that the electrodes which monitor the transfer zone, the storage zone and the control zone are connected to the same input pulse voltage and in that the first and second diode zones are preferably connected to each other and in that in the case of the afflux zone, the depletion zone and the signal zone being monitored by electrodes, these electrodes are preferably connected to direct current voltages and in that in order to carry out an electrical signal input the input pulse voltage conductor is connected to that clock pulse voltage conductor of the CCD shift register which is monitoring the storage zone downstream of the control zone and in that to carry out a reference level input the input pulse voltage conductor is connected to the transfer pulse conductor of the CCD sensor arrangement.

2. Input circuit for charge-coupled devices according to Claim 1, characterized in that the control signal and depletion zones are located in the extended axis of the CCD register, the depletion zone having substantially the same width as the signal zone while the transfer, storage and afflux zones are located laterally of the CCD register.

3. Input circuit for charge-coupled devices according to Claim 1 and 2, characterized in that for a two-phase CCD in which one phase is fed with a clock pulse sequence while the other phase is fed with a direct current voltage, the electrodes monitoring the afflux and depletion zones are connected to the direct current voltage conductor of the CCD shift register.

4. Input circuit for charge-coupled devices according to Claim 1 to 3, characterized in that in order to carry out a two-fold reference level input the entire circuit is disposed laterally of the CCD register and is designed in accordance with the special embodiment shown in Fig. 5.

5. Input circuit for charge-coupled devices as clamed in Claim 1, substantially as described herein with reference to and as illustrated by any one of the examples shown in the accompanging drawings.