DE3530255A1 - Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code - Google Patents

Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code

Info

Publication number
DE3530255A1
DE3530255A1 DE19853530255 DE3530255A DE3530255A1 DE 3530255 A1 DE3530255 A1 DE 3530255A1 DE 19853530255 DE19853530255 DE 19853530255 DE 3530255 A DE3530255 A DE 3530255A DE 3530255 A1 DE3530255 A1 DE 3530255A1
Authority
DE
Germany
Prior art keywords
code
circuit
excess
lines
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19853530255
Other languages
German (de)
Inventor
Paul Merkle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to DE19853530255 priority Critical patent/DE3530255A1/en
Publication of DE3530255A1 publication Critical patent/DE3530255A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/20—Conversion to or from n-out-of-m codes
    • H03M7/22—Conversion to or from n-out-of-m codes to or from one-out-of-m codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)

Abstract

The code conversion circuit according to the subject-matter of the invention differs from other excess-3/1-out-of-10 code conversion circuits in that it has no AND circuits with more than 2 inputs. <IMAGE>

Description

Gegenstand der Erfindung ist eine Umcodierschaltung für die Umcodierung von Exzeß-3-codierten Dezimalziffern in Dezimal- 1-aus-10-codierte Dezimal-Ziffern. Erfindungsgemäß hat diese Umcodierschaltung keine Und-Schaltungen mit 4 Eingängen, sondern nur Und-Schaltungen mit 2 Eingängen und eine Oder- Schaltung mit 7 Eingängen und 3 Negierschaltungen.The invention relates to a recoding circuit for the Recoding of excess 3-coded decimal digits into decimal 1-out-of-10 encoded decimal digits. According to the invention Recoding circuit no AND circuits with 4 inputs, but only AND circuits with 2 inputs and an OR Circuit with 7 inputs and 3 negation circuits.

Diese Exzeß-3-Dezimal-1-aus-10-Umcodierschaltung ist in Fig. 1 dargestellt. In Fig. 2 ist der Dezimal-1-aus-10-Code dar­ gestellt und in Fig. 3 der Exzeß-3-Code.This excess 3 decimal 1 out of 10 recoding circuit is shown in FIG. 1. In Fig. 2 the decimal 1 out of 10 code is shown and in Fig. 3 the excess 3 code.

Diese Exzeß-3-Dezimal-1-aus-10-Umcodierschaltung besteht aus 15 Und-Schaltungen 1 bis 15 mit je 2 Eingängen und der Oder- Schaltung 16 mit 7 Eingängen und 3 Negier-Schaltungen 17 bis 19 und den zugehörigen Leitungen. Die Eingänge M sind mit den Buchstaben A bis D gekennzeichnet. Die Ausgänge N sind mit den zugehörigen Zahlenwerten (Ziffern 0 bis 9) gekenn­ zeichnet.This excess 3 decimal 1 out of 10 recoding circuit consists of 15 AND circuits 1 to 15 with 2 inputs each and the OR circuit 16 with 7 inputs and 3 negation circuits 17 to 19 and the associated lines. The inputs M are marked with the letters A to D. The outputs N are marked with the associated numerical values (digits 0 to 9).

Claims (6)

1. Umcodierschaltung für die Umcodierung von Exzeß-3-co­ dierten Dezimalziffern in dezimal-1-aus-10-codierte Dezimalziffern, dadurch gekennzeichnet, daß sie keine Und-Schaltungen mit 4 Eingängen aufweist.1. transcoding circuit for transcoding excess-3-coded decimal digits into decimal-1-out of 10-coded decimal digits, characterized in that it has no AND circuits with 4 inputs. 2. Umcodierschaltung nach Anspruch 1, dadurch gekennzeich­ net, daß sie 3 Sperr-Schaltungen (21 bis 23) aufweist.2. transcoding circuit according to claim 1, characterized in that it has 3 blocking circuits ( 21 to 23 ). 3. Umcodierschaltung nach Anspruch 1 und 2, dadurch ge­ kennzeichnet, daß von der Sperr-Schaltung (21) die Lei­ tungen für die Ziffern 0 und 1 und 5 gesperrt werden, wenn die Oder-Schaltung (16) an einem ihrer Eingänge H- Potential hat.3. transcoding circuit according to claim 1 and 2, characterized in that the locking lines ( 21 ), the lines for the digits 0 and 1 and 5 are blocked when the OR circuit ( 16 ) at one of its inputs H - Has potential. 4. Umcodierschaltung nach Anspruch 1 bis 3, dadurch gekenn­ zeichnet, daß von der Sperr-Schaltung (22) die Lei­ tungen für die Ziffern 2 und 3 gesperrt werden, wenn die Negierschaltung (18) an ihrem Eingang H-Potential hat.4. transcoding circuit according to claim 1 to 3, characterized in that the locking lines ( 22 ), the lines for the numbers 2 and 3 are blocked when the negating circuit ( 18 ) has H potential at its input. 5. Umcodierschaltung nach Anspruch 1 bis 4, dadurch gekenn­ zeichnet, daß von der Sperr-Schaltung ( 23) die Lei­ tungen für die Ziffern 6 und 7 gesperrt werden, wenn die Negier-Schaltung (19) an ihrem Eingang H-Potential hat.5. transcoding circuit according to claim 1 to 4, characterized in that the locking lines ( 23 ), the lines for the digits 6 and 7 are blocked when the negating circuit ( 19 ) has H potential at its input. 6. Umcodierschaltung nach Anspruch 1 oder nach Anspruch 1 und 2 oder nach Anspruch 1 bis 5, dadurch gekennzeichnet, daß sie aus 15 Und-Schaltungen (1 bis 15) mit je 2 Ein­ gängen und einer Oder-Schaltung (16) mit 7 Eingängen und 3 Negier-Schaltungen (17 bis 19) und den zugehörigen Leitungen besteht.6. recoding circuit according to claim 1 or according to claim 1 and 2 or according to claim 1 to 5, characterized in that it consists of 15 AND circuits ( 1 to 15 ) each with 2 A gears and an OR circuit ( 16 ) with 7 inputs and 3 Negier circuits ( 17 to 19 ) and the associated lines.
DE19853530255 1985-08-23 1985-08-23 Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code Withdrawn DE3530255A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19853530255 DE3530255A1 (en) 1985-08-23 1985-08-23 Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19853530255 DE3530255A1 (en) 1985-08-23 1985-08-23 Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code

Publications (1)

Publication Number Publication Date
DE3530255A1 true DE3530255A1 (en) 1987-03-12

Family

ID=6279248

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853530255 Withdrawn DE3530255A1 (en) 1985-08-23 1985-08-23 Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code

Country Status (1)

Country Link
DE (1) DE3530255A1 (en)

Similar Documents

Publication Publication Date Title
DE3530255A1 (en) Code conversion circuit for the conversion of excess-three code into decimal one-out-of-ten code
DE3530208A1 (en) Code conversion circuit for the conversion of BCD-8421 code into decimal one-out-of-ten code
DE3530209A1 (en) Code conversion circuit for the conversion of Aiken code into decimal one-out-of-ten code
DE3538134A1 (en) Code-converting circuit for code conversion from 5211 code into decimal 1-out-of-10 code
DE3530224A1 (en) Code conversion for the conversion of a four-field code into decimal one-out-of-ten code
DE3538691A1 (en) Code-converting circuit for code conversion from 5211 code into decimal 1-out-of-10 code
DE3622718A1 (en) Code conversion circuit to convert 51111 code into decimal 1-out-of-10 code
DE3621887A1 (en) Code conversion circuit to convert 54321 code into decimal 1-out-of-10 code
DE3708502A1 (en) Code conversion circuit for converting decimal digits from 51111 code to 5211 code
DE2554881C3 (en) Circuit arrangement for converting a two-digit, binary-coded number into a pure binary number
DE3642071A1 (en) Recoding circuit for recoding decimal digits from 5211 code into the 54321 code
DE3700312A1 (en) Code conversion circuit to convert decimal digits from 5211 code to 1-out-of-10 code
DE3703177A1 (en) Code conversion circuit, using which decimal digits are converted from 51111 code to 5211 code and from 54321 code to 5211 code
DE3530455A1 (en) Code conversion circuit combined with negator complement circuit
DE3616928A1 (en) Adder circuit in decimal 1-out-of-10 code
DE3615709A1 (en) Adder circuit in decimal 1-out-of-10 code
DE3624694A1 (en) Exchange circuit in decimal 1-out-of-10 code
DE3533033A1 (en) Code-converting circuit for code conversion from a 4-field code into decimal 1-out-of-10 code
DE3618592A1 (en) Partial summand conversion circuit for adder circuits in decimal 1-out-of-10 code
DE3710295A1 (en) Adder circuit in 5211 code
DE3721555A1 (en) Adder circuit in 51111 code
DE3624620A1 (en) Adder circuit in decimal 1-out-of-10 code
DE3628831A1 (en) Adder circuit using decimal 1-out-of-10 code
DE3627216A1 (en) Adder circuit using 51111 code
DE3622729A1 (en) Adder circuit in 54321 code

Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee