DE3502147C2 - - Google Patents
Info
- Publication number
- DE3502147C2 DE3502147C2 DE3502147A DE3502147A DE3502147C2 DE 3502147 C2 DE3502147 C2 DE 3502147C2 DE 3502147 A DE3502147 A DE 3502147A DE 3502147 A DE3502147 A DE 3502147A DE 3502147 C2 DE3502147 C2 DE 3502147C2
- Authority
- DE
- Germany
- Prior art keywords
- memory
- data
- signal
- read
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59008572A JPH0630074B2 (ja) | 1984-01-23 | 1984-01-23 | プロセッサ |
JP59110764A JPH06100984B2 (ja) | 1984-06-01 | 1984-06-01 | マイクロプロセッサ |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3502147A1 DE3502147A1 (de) | 1985-08-08 |
DE3502147C2 true DE3502147C2 (US08197722-20120612-C00042.png) | 1987-10-01 |
Family
ID=26343109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19853502147 Granted DE3502147A1 (de) | 1984-01-23 | 1985-01-23 | Datenverarbeitungssystem mit verbesserter pufferspeichersteuerung |
Country Status (2)
Country | Link |
---|---|
US (7) | US5148526A (US08197722-20120612-C00042.png) |
DE (1) | DE3502147A1 (US08197722-20120612-C00042.png) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5838946A (en) * | 1990-04-14 | 1998-11-17 | Sun Microsystems, Inc. | Method and apparatus for accomplishing processor read of selected information through a cache memory |
JP3169599B2 (ja) * | 1990-08-03 | 2001-05-28 | 株式会社日立製作所 | 半導体装置、その駆動方法、その読み出し方法 |
US5259803A (en) * | 1991-04-09 | 1993-11-09 | Lyman Ronald L | Toy construction set featuring gears and radiant connectors |
EP0598570B1 (en) * | 1992-11-13 | 2000-01-19 | National Semiconductor Corporation | Microprocessor comprising region configuration system and method for controlling memory subsystem operations by address region |
JP3230898B2 (ja) * | 1993-06-02 | 2001-11-19 | シャープ株式会社 | データ駆動型情報処理システム |
JP2634141B2 (ja) * | 1994-01-19 | 1997-07-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | マルチプロセッサ・システム |
US5900014A (en) * | 1994-12-08 | 1999-05-04 | Ast Research, Inc. | External means of overriding and controlling cacheability attribute of selected CPU accesses to monitor instruction and data streams |
US5983025A (en) * | 1995-06-07 | 1999-11-09 | International Business Machines Corporation | Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses |
GB2302604B (en) * | 1995-06-23 | 2000-02-16 | Advanced Risc Mach Ltd | Data memory access control |
JPH0916472A (ja) * | 1995-07-04 | 1997-01-17 | Fujitsu Ltd | キャッシュメモリ試験方法 |
JP3123413B2 (ja) * | 1995-11-07 | 2001-01-09 | 株式会社日立製作所 | コンピュータシステム |
KR0174711B1 (ko) * | 1996-04-24 | 1999-04-15 | 김광호 | 하드디스크 캐시의 제어방법 |
US6298355B1 (en) * | 1996-09-20 | 2001-10-02 | Hitachi, Ltd. | Computer system |
US5870109A (en) * | 1997-06-06 | 1999-02-09 | Digital Equipment Corporation | Graphic system with read/write overlap detector |
US6014737A (en) * | 1997-11-19 | 2000-01-11 | Sony Corporation Of Japan | Method and system for allowing a processor to perform read bypassing while automatically maintaining input/output data integrity |
JP2000181796A (ja) * | 1998-12-14 | 2000-06-30 | Nec Corp | 情報処理装置 |
US20050268019A1 (en) * | 2004-06-01 | 2005-12-01 | Che-Hui Chang Chien | [interface and system for transmitting real-time data ] |
KR100792213B1 (ko) * | 2005-08-11 | 2008-01-07 | 삼성전자주식회사 | 메모리 컨트롤러와 메모리를 인터페이싱하는 랩퍼 회로 |
US8510509B2 (en) * | 2007-12-18 | 2013-08-13 | International Business Machines Corporation | Data transfer to memory over an input/output (I/O) interconnect |
US20090327564A1 (en) * | 2008-06-30 | 2009-12-31 | Nagabhushan Chitlur | Method and apparatus of implementing control and status registers using coherent system memory |
CN104317728B (zh) * | 2014-10-13 | 2018-03-23 | 大唐移动通信设备有限公司 | 一种安全复位存储设备的方法和装置 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3845474A (en) * | 1973-11-05 | 1974-10-29 | Honeywell Inf Systems | Cache store clearing operation for multiprocessor mode |
US4055851A (en) * | 1976-02-13 | 1977-10-25 | Digital Equipment Corporation | Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle |
US4075686A (en) * | 1976-12-30 | 1978-02-21 | Honeywell Information Systems Inc. | Input/output cache system including bypass capability |
US4136386A (en) * | 1977-10-06 | 1979-01-23 | International Business Machines Corporation | Backing store access coordination in a multi-processor system |
US4167782A (en) * | 1977-12-22 | 1979-09-11 | Honeywell Information Systems Inc. | Continuous updating of cache store |
US4161024A (en) * | 1977-12-22 | 1979-07-10 | Honeywell Information Systems Inc. | Private cache-to-CPU interface in a bus oriented data processing system |
JPS54128634A (en) * | 1978-03-30 | 1979-10-05 | Toshiba Corp | Cash memory control system |
US4197580A (en) * | 1978-06-08 | 1980-04-08 | Bell Telephone Laboratories, Incorporated | Data processing system including a cache memory |
US4264953A (en) * | 1979-03-30 | 1981-04-28 | Honeywell Inc. | Virtual cache |
US4467421A (en) * | 1979-10-18 | 1984-08-21 | Storage Technology Corporation | Virtual storage system and method |
US4322795A (en) * | 1980-01-24 | 1982-03-30 | Honeywell Information Systems Inc. | Cache memory utilizing selective clearing and least recently used updating |
US4323967A (en) * | 1980-04-15 | 1982-04-06 | Honeywell Information Systems Inc. | Local bus interface for controlling information transfers between units in a central subsystem |
US4371928A (en) * | 1980-04-15 | 1983-02-01 | Honeywell Information Systems Inc. | Interface for controlling information transfers between main data processing systems units and a central subsystem |
JPS5714636A (en) * | 1980-06-13 | 1982-01-25 | Exxon Research Engineering Co | Chlorinated butyl rubber/brominated butyl rubber blend compound with improved adhesive properties |
US4399506A (en) * | 1980-10-06 | 1983-08-16 | International Business Machines Corporation | Store-in-cache processor means for clearing main storage |
US4445170A (en) * | 1981-03-19 | 1984-04-24 | Zilog, Inc. | Computer segmented memory management technique wherein two expandable memory portions are contained within a single segment |
US4410944A (en) * | 1981-03-24 | 1983-10-18 | Burroughs Corporation | Apparatus and method for maintaining cache memory integrity in a shared memory environment |
US4445174A (en) * | 1981-03-31 | 1984-04-24 | International Business Machines Corporation | Multiprocessing system including a shared cache |
JPS5848289A (ja) * | 1981-09-17 | 1983-03-22 | Fuji Electric Co Ltd | バツフアメモリ制御方式 |
DE3382152D1 (de) * | 1982-12-09 | 1991-03-07 | Sequoia Systems Inc | Sicherstellungsspeichersystem. |
US4467921A (en) * | 1983-04-08 | 1984-08-28 | Colgate-Palmolive Company | Visually clear dentifrice |
-
1985
- 1985-01-23 DE DE19853502147 patent/DE3502147A1/de active Granted
-
1988
- 1988-04-08 US US07/183,401 patent/US5148526A/en not_active Expired - Lifetime
-
1991
- 1991-12-11 US US07/804,739 patent/US5479625A/en not_active Expired - Lifetime
-
1995
- 1995-03-29 US US08/413,110 patent/US5502825A/en not_active Expired - Lifetime
- 1995-05-05 US US08/435,958 patent/US5509133A/en not_active Expired - Lifetime
-
1996
- 1996-05-17 US US08/649,333 patent/US5619677A/en not_active Expired - Fee Related
-
1997
- 1997-02-06 US US08/795,639 patent/US5822761A/en not_active Expired - Fee Related
-
1998
- 1998-06-01 US US09/087,900 patent/US6381680B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6381680B1 (en) | 2002-04-30 |
US5479625A (en) | 1995-12-26 |
US5619677A (en) | 1997-04-08 |
DE3502147A1 (de) | 1985-08-08 |
US5822761A (en) | 1998-10-13 |
US5502825A (en) | 1996-03-26 |
US5148526A (en) | 1992-09-15 |
US5509133A (en) | 1996-04-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition |