DE3484986D1 - Cmos-redundanzschaltung mit nulleistung. - Google Patents

Cmos-redundanzschaltung mit nulleistung.

Info

Publication number
DE3484986D1
DE3484986D1 DE8484630216T DE3484986T DE3484986D1 DE 3484986 D1 DE3484986 D1 DE 3484986D1 DE 8484630216 T DE8484630216 T DE 8484630216T DE 3484986 T DE3484986 T DE 3484986T DE 3484986 D1 DE3484986 D1 DE 3484986D1
Authority
DE
Germany
Prior art keywords
cmos
zero power
redundancy circuit
redundancy
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484630216T
Other languages
German (de)
English (en)
Inventor
Ching-Lin Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE3484986D1 publication Critical patent/DE3484986D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00392—Modifications for increasing the reliability for protection by circuit redundancy

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Electronic Switches (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8484630216T 1984-01-06 1984-12-28 Cmos-redundanzschaltung mit nulleistung. Expired - Lifetime DE3484986D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/568,960 US4613959A (en) 1984-01-06 1984-01-06 Zero power CMOS redundancy circuit

Publications (1)

Publication Number Publication Date
DE3484986D1 true DE3484986D1 (de) 1991-10-02

Family

ID=24273480

Family Applications (2)

Application Number Title Priority Date Filing Date
DE8484630216T Expired - Lifetime DE3484986D1 (de) 1984-01-06 1984-12-28 Cmos-redundanzschaltung mit nulleistung.
DE198484630216T Pending DE148722T1 (de) 1984-01-06 1984-12-28 Cmos-redundanzschaltung mit nulleistung.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE198484630216T Pending DE148722T1 (de) 1984-01-06 1984-12-28 Cmos-redundanzschaltung mit nulleistung.

Country Status (4)

Country Link
US (1) US4613959A (enExample)
EP (1) EP0148722B1 (enExample)
JP (1) JPS60170100A (enExample)
DE (2) DE3484986D1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837520A (en) * 1985-03-29 1989-06-06 Honeywell Inc. Fuse status detection circuit
JPH0620100B2 (ja) * 1985-11-14 1994-03-16 日本電気株式会社 半導体集積回路の調整方法
US4714839A (en) * 1986-03-27 1987-12-22 Advanced Micro Devices, Inc. Control circuit for disabling or enabling the provision of redundancy
JPS62250600A (ja) * 1986-04-22 1987-10-31 Sharp Corp 半導体集積回路装置
JPS632351A (ja) * 1986-06-20 1988-01-07 Sharp Corp 半導体装置
US4689494A (en) * 1986-09-18 1987-08-25 Advanced Micro Devices, Inc. Redundancy enable/disable circuit
JPS63100818A (ja) * 1986-10-17 1988-05-02 Nec Corp 半導体装置
US4716302A (en) * 1986-12-22 1987-12-29 Motorola, Inc. Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal
US4855613A (en) * 1987-05-08 1989-08-08 Mitsubishi Denki Kabushiki Kaisha Wafer scale integration semiconductor device having improved chip power-supply connection arrangement
US4806793A (en) * 1987-10-02 1989-02-21 Motorola, Inc. Signature circuit responsive to an input signal
US4908525A (en) * 1989-02-03 1990-03-13 The United States Of America As Represented By The Secretary Of The Air Force Cut-only CMOS switch for discretionary connect and disconnect
US4996670A (en) * 1989-09-28 1991-02-26 International Business Machines Corporation Zero standby power, radiation hardened, memory redundancy circuit
US5038368A (en) * 1990-02-02 1991-08-06 David Sarnoff Research Center, Inc. Redundancy control circuit employed with various digital logic systems including shift registers
US5327381A (en) * 1992-06-03 1994-07-05 Mips Computer Systems, Inc. Redundancy selection apparatus and method for an array
US5740350A (en) * 1995-06-30 1998-04-14 Bull Hn Information Systems Inc. Reconfigurable computer system
US5731734A (en) * 1996-10-07 1998-03-24 Atmel Corporation Zero power fuse circuit
US6054893A (en) * 1997-04-10 2000-04-25 Institute Of Microelectronics Low current differential fuse circuit
US6229378B1 (en) * 1997-12-31 2001-05-08 Intel Corporation Using programmable jumpers to set an IC device's bit-encoded output during manufacturing and testing
US5999038A (en) * 1998-09-24 1999-12-07 Atmel Corporation Fuse circuit having zero power draw for partially blown condition
US6469499B2 (en) * 2001-02-06 2002-10-22 Delphi Technologies, Inc. Apparatus and method for low power position sensing systems
WO2005015567A1 (de) * 2003-07-29 2005-02-17 Infineon Technologies Ag Nichtflüchtiges speicherelement mit erhöhter datensicherheit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4346459A (en) * 1980-06-30 1982-08-24 Inmos Corporation Redundancy scheme for an MOS memory
JPS58177599A (ja) * 1982-04-12 1983-10-18 Toshiba Corp 半導体集積回路装置
US4546455A (en) * 1981-12-17 1985-10-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device

Also Published As

Publication number Publication date
DE148722T1 (de) 1985-11-07
US4613959A (en) 1986-09-23
EP0148722B1 (en) 1991-08-28
JPH058520B2 (enExample) 1993-02-02
JPS60170100A (ja) 1985-09-03
EP0148722A2 (en) 1985-07-17
EP0148722A3 (en) 1988-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SGS-THOMSON MICROELECTRONICS INC. (N.D.GES.DES STA

8339 Ceased/non-payment of the annual fee