DE3481103D1 - Verfahren zum untereinander verbinden von metallschichten. - Google Patents

Verfahren zum untereinander verbinden von metallschichten.

Info

Publication number
DE3481103D1
DE3481103D1 DE8484903413T DE3481103T DE3481103D1 DE 3481103 D1 DE3481103 D1 DE 3481103D1 DE 8484903413 T DE8484903413 T DE 8484903413T DE 3481103 T DE3481103 T DE 3481103T DE 3481103 D1 DE3481103 D1 DE 3481103D1
Authority
DE
Germany
Prior art keywords
metal layers
joining metal
joining
layers
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484903413T
Other languages
English (en)
Inventor
S Gwozdz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3481103D1 publication Critical patent/DE3481103D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8484903413T 1983-09-07 1984-09-06 Verfahren zum untereinander verbinden von metallschichten. Expired - Lifetime DE3481103D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/529,920 US4451326A (en) 1983-09-07 1983-09-07 Method for interconnecting metallic layers
PCT/US1984/001432 WO1985001020A1 (en) 1983-09-07 1984-09-06 Method for interconnecting metallic layers

Publications (1)

Publication Number Publication Date
DE3481103D1 true DE3481103D1 (de) 1990-02-22

Family

ID=24111749

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484903413T Expired - Lifetime DE3481103D1 (de) 1983-09-07 1984-09-06 Verfahren zum untereinander verbinden von metallschichten.

Country Status (5)

Country Link
US (1) US4451326A (de)
EP (1) EP0154650B1 (de)
JP (1) JPH0732153B2 (de)
DE (1) DE3481103D1 (de)
WO (1) WO1985001020A1 (de)

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US4576900A (en) * 1981-10-09 1986-03-18 Amdahl Corporation Integrated circuit multilevel interconnect system and method
GB2116363B (en) * 1982-03-03 1985-10-16 Philips Electronic Associated Multi-level infra-red detectors and their manufacture
US4617193A (en) * 1983-06-16 1986-10-14 Digital Equipment Corporation Planar interconnect for integrated circuits
US4600624A (en) * 1983-09-20 1986-07-15 International Business Machines Corporation Composite insulator structure
US4601939A (en) * 1983-09-20 1986-07-22 International Business Machines Corporation Composite insulator structure
JPS60116167A (ja) * 1983-11-29 1985-06-22 Toshiba Corp 半導体記憶装置及びその製造方法
KR900004968B1 (ko) * 1984-02-10 1990-07-12 후지쓰 가부시끼가이샤 반도체장치 제조방법
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures
EP0177845A1 (de) * 1984-09-28 1986-04-16 Siemens Aktiengesellschaft Integrierter Schaltkreis mit Mehrlagenverdrahtung und Verfahren zu seiner Herstellung
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4605470A (en) * 1985-06-10 1986-08-12 Advanced Micro Devices, Inc. Method for interconnecting conducting layers of an integrated circuit device
US4655874A (en) * 1985-07-26 1987-04-07 Advanced Micro Devices, Inc. Process for smoothing a non-planar surface
US4662064A (en) * 1985-08-05 1987-05-05 Rca Corporation Method of forming multi-level metallization
US4666553A (en) * 1985-08-28 1987-05-19 Rca Corporation Method for planarizing multilayer semiconductor devices
FR2588417B1 (fr) * 1985-10-03 1988-07-29 Bull Sa Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant
US4898838A (en) * 1985-10-16 1990-02-06 Texas Instruments Incorporated Method for fabricating a poly emitter logic array
US4799992A (en) * 1985-10-31 1989-01-24 Texas Instruments Incorporated Interlevel dielectric fabrication process
US5114530A (en) * 1985-10-31 1992-05-19 Texas Instruments Incorporated Interlevel dielectric process
EP0245290A1 (de) * 1985-11-04 1987-11-19 Motorola, Inc. Dielektrikum aus intermetallischem glas
US4642162A (en) * 1986-01-02 1987-02-10 Honeywell Inc. Planarization of dielectric layers in integrated circuits
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
JPS6318697A (ja) * 1986-07-11 1988-01-26 日本電気株式会社 多層配線基板
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
US4721689A (en) * 1986-08-28 1988-01-26 International Business Machines Corporation Method for simultaneously forming an interconnection level and via studs
USRE33622E (en) * 1986-09-04 1991-06-25 At&T Bell Laboratories Integrated circuits having stepped dielectric regions
US4999318A (en) * 1986-11-12 1991-03-12 Hitachi, Ltd. Method for forming metal layer interconnects using stepped via walls
US4824521A (en) * 1987-04-01 1989-04-25 Fairchild Semiconductor Corporation Planarization of metal pillars on uneven substrates
JPH01138734A (ja) * 1987-11-25 1989-05-31 Mitsubishi Electric Corp 複導電体層を有する半導体装置およびその製造方法
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
US5084404A (en) * 1988-03-31 1992-01-28 Advanced Micro Devices Gate array structure and process to allow optioning at second metal mask only
US5023701A (en) * 1988-03-31 1991-06-11 Advanced Micro Devices, Inc. Gate array structure and process to allow optioning at second metal mask only
JPH0797602B2 (ja) * 1988-05-06 1995-10-18 日本電気株式会社 半導体集積回路装置
US5136344A (en) * 1988-11-02 1992-08-04 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
US5354386A (en) * 1989-03-24 1994-10-11 National Semiconductor Corporation Method for plasma etching tapered and stepped vias
US5000818A (en) * 1989-08-14 1991-03-19 Fairchild Semiconductor Corporation Method of fabricating a high performance interconnect system for an integrated circuit
US5055426A (en) * 1990-09-10 1991-10-08 Micron Technology, Inc. Method for forming a multilevel interconnect structure on a semiconductor wafer
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
US5453401A (en) * 1991-05-01 1995-09-26 Motorola, Inc. Method for reducing corrosion of a metal surface containing at least aluminum and copper
US5641703A (en) * 1991-07-25 1997-06-24 Massachusetts Institute Of Technology Voltage programmable links for integrated circuits
US5252382A (en) * 1991-09-03 1993-10-12 Cornell Research Foundation, Inc. Interconnect structures having patterned interfaces to minimize stress migration and related electromigration damages
JPH0574958A (ja) * 1991-09-13 1993-03-26 Nec Corp 半導体装置およびその製造方法
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5702870A (en) * 1993-08-27 1997-12-30 Vlsi Technology, Inc. Integrated-circuit via formation using gradient photolithography
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US5420063A (en) * 1994-04-11 1995-05-30 National Semiconductor Corporation Method of producing a resistor in an integrated circuit
JP3123450B2 (ja) * 1996-11-26 2001-01-09 日本電気株式会社 半導体装置およびその製造方法
US5883006A (en) * 1997-12-12 1999-03-16 Kabushiki Kaisha Toshiba Method for making a semiconductor device using a flowable oxide film
US7012811B1 (en) 2000-05-10 2006-03-14 Micron Technology, Inc. Method of tuning a multi-path circuit
US20040018733A1 (en) * 2002-07-23 2004-01-29 Hak Baek Jae Method of planarizing a surface of a semiconductor wafer
TWI302349B (en) * 2006-01-04 2008-10-21 Promos Technologies Inc Metal etching process and rework method thereof
CN102315087A (zh) * 2010-06-30 2012-01-11 财团法人工业技术研究院 表面处理装置及其方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
DE2638799C3 (de) * 1976-08-27 1981-12-03 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur Verbesserung der Haftung von metallischen Leiterzügen auf Polyimidschichten in integrierten Schaltungen
US4164461A (en) * 1977-01-03 1979-08-14 Raytheon Company Semiconductor integrated circuit structures and manufacturing methods
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
DE3060913D1 (en) * 1979-05-12 1982-11-11 Fujitsu Ltd Improvement in method of manufacturing electronic device having multilayer wiring structure
IE52971B1 (en) * 1979-07-23 1988-04-27 Fujitsu Ltd Method of manufacturing a semiconductor device wherein first and second layers are formed
EP0049400B1 (de) * 1980-09-22 1984-07-11 Kabushiki Kaisha Toshiba Verfahren zum Glätten einer isolierenden Schicht auf einem Halbleiterkörper
US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits

Also Published As

Publication number Publication date
EP0154650A4 (de) 1986-09-15
JPS60502179A (ja) 1985-12-12
EP0154650A1 (de) 1985-09-18
WO1985001020A1 (en) 1985-03-14
US4451326A (en) 1984-05-29
EP0154650B1 (de) 1990-01-17
JPH0732153B2 (ja) 1995-04-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee