DE3479173D1 - A single mask process for implanting self-aligned source and drain electrodes to form a cmos structure - Google Patents
A single mask process for implanting self-aligned source and drain electrodes to form a cmos structureInfo
- Publication number
- DE3479173D1 DE3479173D1 DE8484111287T DE3479173T DE3479173D1 DE 3479173 D1 DE3479173 D1 DE 3479173D1 DE 8484111287 T DE8484111287 T DE 8484111287T DE 3479173 T DE3479173 T DE 3479173T DE 3479173 D1 DE3479173 D1 DE 3479173D1
- Authority
- DE
- Germany
- Prior art keywords
- drain electrodes
- mask process
- cmos structure
- single mask
- aligned source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/539,516 US4509991A (en) | 1983-10-06 | 1983-10-06 | Single mask process for fabricating CMOS structure |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3479173D1 true DE3479173D1 (en) | 1989-08-31 |
Family
ID=24151557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484111287T Expired DE3479173D1 (en) | 1983-10-06 | 1984-09-21 | A single mask process for implanting self-aligned source and drain electrodes to form a cmos structure |
Country Status (4)
Country | Link |
---|---|
US (1) | US4509991A (de) |
EP (1) | EP0136632B1 (de) |
JP (1) | JPS6052594B2 (de) |
DE (1) | DE3479173D1 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4698899A (en) * | 1983-10-19 | 1987-10-13 | Gould Inc. | Field effect transistor |
US4621276A (en) * | 1984-05-24 | 1986-11-04 | Texas Instruments Incorporated | Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4578859A (en) * | 1984-08-22 | 1986-04-01 | Harris Corporation | Implant mask reversal process |
US4600445A (en) * | 1984-09-14 | 1986-07-15 | International Business Machines Corporation | Process for making self aligned field isolation regions in a semiconductor substrate |
US4584027A (en) * | 1984-11-07 | 1986-04-22 | Ncr Corporation | Twin well single mask CMOS process |
JPS61127174A (ja) * | 1984-11-26 | 1986-06-14 | Toshiba Corp | 半導体装置の製造方法 |
US4604790A (en) * | 1985-04-01 | 1986-08-12 | Advanced Micro Devices, Inc. | Method of fabricating integrated circuit structure having CMOS and bipolar devices |
US4767721A (en) * | 1986-02-10 | 1988-08-30 | Hughes Aircraft Company | Double layer photoresist process for well self-align and ion implantation masking |
US4728617A (en) * | 1986-11-04 | 1988-03-01 | Intel Corporation | Method of fabricating a MOSFET with graded source and drain regions |
JPS63133564A (ja) * | 1986-11-25 | 1988-06-06 | Nec Corp | 半導体集積回路の製造方法 |
US4881105A (en) * | 1988-06-13 | 1989-11-14 | International Business Machines Corporation | Integrated trench-transistor structure and fabrication process |
US5182218A (en) * | 1991-02-25 | 1993-01-26 | Sumitomo Electric Industries, Ltd. | Production methods for compound semiconductor device having lightly doped drain structure |
US5132236A (en) * | 1991-07-30 | 1992-07-21 | Micron Technology, Inc. | Method of semiconductor manufacture using an inverse self-aligned mask |
JPH05102068A (ja) * | 1991-10-11 | 1993-04-23 | Kobe Steel Ltd | ダイヤモンドを用いた電子デバイスの電極形成方法 |
US5956583A (en) * | 1997-06-30 | 1999-09-21 | Fuller; Robert T. | Method for forming complementary wells and self-aligned trench with a single mask |
US6107148A (en) * | 1998-10-26 | 2000-08-22 | Nippon Steel Semiconductor Corporation | Method for fabricating a semiconductor device |
JP2001313390A (ja) * | 2000-02-29 | 2001-11-09 | Agere Systems Inc | 半導体材料における選択的レーザ・アニール |
CN102097377A (zh) * | 2009-12-10 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制作方法 |
US8372737B1 (en) * | 2011-06-28 | 2013-02-12 | Varian Semiconductor Equipment Associates, Inc. | Use of a shadow mask and a soft mask for aligned implants in solar cells |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4033797A (en) * | 1973-05-21 | 1977-07-05 | Hughes Aircraft Company | Method of manufacturing a complementary metal-insulation-semiconductor circuit |
US4027380A (en) * | 1974-06-03 | 1977-06-07 | Fairchild Camera And Instrument Corporation | Complementary insulated gate field effect transistor structure and process for fabricating the structure |
JPS54140483A (en) * | 1978-04-21 | 1979-10-31 | Nec Corp | Semiconductor device |
US4402761A (en) * | 1978-12-15 | 1983-09-06 | Raytheon Company | Method of making self-aligned gate MOS device having small channel lengths |
US4244752A (en) * | 1979-03-06 | 1981-01-13 | Burroughs Corporation | Single mask method of fabricating complementary integrated circuits |
US4235011A (en) * | 1979-03-28 | 1980-11-25 | Honeywell Inc. | Semiconductor apparatus |
DE2947350A1 (de) * | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie |
US4366613A (en) * | 1980-12-17 | 1983-01-04 | Ibm Corporation | Method of fabricating an MOS dynamic RAM with lightly doped drain |
US4382827A (en) * | 1981-04-27 | 1983-05-10 | Ncr Corporation | Silicon nitride S/D ion implant mask in CMOS device fabrication |
JPS5832447A (ja) * | 1981-08-20 | 1983-02-25 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS5843556A (ja) * | 1981-09-08 | 1983-03-14 | Toshiba Corp | 相補型半導体装置の製造方法 |
US4435896A (en) * | 1981-12-07 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Method for fabricating complementary field effect transistor devices |
DE3149185A1 (de) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
-
1983
- 1983-10-06 US US06/539,516 patent/US4509991A/en not_active Expired - Lifetime
-
1984
- 1984-07-18 JP JP59147701A patent/JPS6052594B2/ja not_active Expired
- 1984-09-21 DE DE8484111287T patent/DE3479173D1/de not_active Expired
- 1984-09-21 EP EP84111287A patent/EP0136632B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6080269A (ja) | 1985-05-08 |
EP0136632A3 (en) | 1986-12-30 |
US4509991A (en) | 1985-04-09 |
EP0136632B1 (de) | 1989-07-26 |
JPS6052594B2 (ja) | 1985-11-20 |
EP0136632A2 (de) | 1985-04-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |