DE3476842D1 - Integrated circuit processing methods - Google Patents

Integrated circuit processing methods

Info

Publication number
DE3476842D1
DE3476842D1 DE8484301966T DE3476842T DE3476842D1 DE 3476842 D1 DE3476842 D1 DE 3476842D1 DE 8484301966 T DE8484301966 T DE 8484301966T DE 3476842 T DE3476842 T DE 3476842T DE 3476842 D1 DE3476842 D1 DE 3476842D1
Authority
DE
Germany
Prior art keywords
integrated circuit
processing methods
circuit processing
methods
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484301966T
Other languages
English (en)
Inventor
Stephen James Rhodes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Caldicot Ltd
Original Assignee
Plessey Overseas Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Ltd filed Critical Plessey Overseas Ltd
Application granted granted Critical
Publication of DE3476842D1 publication Critical patent/DE3476842D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE8484301966T 1983-04-06 1984-03-23 Integrated circuit processing methods Expired DE3476842D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08309341A GB2137808A (en) 1983-04-06 1983-04-06 Integrated circuit processing method

Publications (1)

Publication Number Publication Date
DE3476842D1 true DE3476842D1 (en) 1989-03-30

Family

ID=10540713

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484301966T Expired DE3476842D1 (en) 1983-04-06 1984-03-23 Integrated circuit processing methods

Country Status (6)

Country Link
US (1) US4536249A (de)
EP (1) EP0122078B1 (de)
JP (1) JPS59197139A (de)
CA (1) CA1215788A (de)
DE (1) DE3476842D1 (de)
GB (1) GB2137808A (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8316477D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
US4924287A (en) * 1985-01-20 1990-05-08 Avner Pdahtzur Personalizable CMOS gate array device and technique
US4675984A (en) * 1985-09-19 1987-06-30 Rca Corporation Method of exposing only the top surface of a mesa
JPS6276653A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体集積回路
US4892635A (en) * 1986-06-26 1990-01-09 American Telephone And Telegraph Company At&T Bell Laboratories Pattern transfer process utilizing multilevel resist structure for fabricating integrated-circuit devices
US5069749A (en) * 1986-07-29 1991-12-03 Digital Equipment Corporation Method of fabricating interconnect layers on an integrated circuit chip using seed-grown conductors
US5329152A (en) * 1986-11-26 1994-07-12 Quick Technologies Ltd. Ablative etch resistant coating for laser personalization of integrated circuits
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
US5008730A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Contact stud structure for semiconductor devices
JPH02100213A (ja) * 1988-10-06 1990-04-12 Alps Electric Co Ltd キートップの製造方法
US5166101A (en) * 1989-09-28 1992-11-24 Applied Materials, Inc. Method for forming a boron phosphorus silicate glass composite layer on a semiconductor wafer
US5314845A (en) * 1989-09-28 1994-05-24 Applied Materials, Inc. Two step process for forming void-free oxide layer over stepped surface of semiconductor wafer
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
CA2137861A1 (en) * 1994-02-21 1995-08-22 Walter Schmidt Process for the production of structures
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
GB2350931B (en) * 1997-06-27 2001-03-14 Nec Corp Method of manufacturing semiconductor device having multilayer wiring
US6548224B1 (en) * 2000-03-07 2003-04-15 Kulicke & Soffa Holdings, Inc. Wiring substrate features having controlled sidewall profiles
CN115132591B (zh) * 2022-09-02 2022-11-29 盛合晶微半导体(江阴)有限公司 聚酰亚胺过孔及晶圆级半导体封装结构的制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3816196A (en) * 1971-06-07 1974-06-11 Gen Electric Passivation of photoresist materials used in selective plasma etching
JPS5144871B2 (de) * 1971-09-25 1976-12-01
JPS49114381A (de) * 1973-02-12 1974-10-31
US4113550A (en) * 1974-08-23 1978-09-12 Hitachi, Ltd. Method for fabricating semiconductor device and etchant for polymer resin
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
GB1576055A (en) * 1976-04-29 1980-10-01 Ibm Formation of patterns of one material surrounded by another material on a substrate
US4070501A (en) * 1976-10-28 1978-01-24 Ibm Corporation Forming self-aligned via holes in thin film interconnection systems
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
US4209356A (en) * 1978-10-18 1980-06-24 General Electric Company Selective etching of polymeric materials embodying silicones via reactor plasmas
JPS56125856A (en) * 1980-03-07 1981-10-02 Fujitsu Ltd Manufacture of semiconductor device
JPS56125855A (en) * 1980-03-07 1981-10-02 Fujitsu Ltd Manufacture of semiconductor device
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4317700A (en) * 1980-08-20 1982-03-02 Rockwell International Corporation Method of fabrication of planar bubble domain device structures
US4409319A (en) * 1981-07-15 1983-10-11 International Business Machines Corporation Electron beam exposed positive resist mask process
US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide

Also Published As

Publication number Publication date
US4536249A (en) 1985-08-20
EP0122078A3 (en) 1986-02-26
JPH0519818B2 (de) 1993-03-17
GB2137808A (en) 1984-10-10
EP0122078A2 (de) 1984-10-17
JPS59197139A (ja) 1984-11-08
EP0122078B1 (de) 1989-02-22
CA1215788A (en) 1986-12-23

Similar Documents

Publication Publication Date Title
GB2134708B (en) Integrated circuits
GB8425824D0 (en) Large scale integrated circuit
GB8402650D0 (en) Circuit
GB8430050D0 (en) Circuit arrangements
GB8422999D0 (en) Circuit arrangement
GB8401959D0 (en) Integrated circuit
GB8412737D0 (en) Circuit arrangement
DE3476842D1 (en) Integrated circuit processing methods
GB8428805D0 (en) Circuit arrangement
GB2144302B (en) Signal processing circuit
EP0142081A3 (en) Signal processing circuit
GB8327868D0 (en) Integrated circuits
GB8431766D0 (en) Circuit arrangement
GB8410849D0 (en) Circuit
EP0140744A3 (en) Integrated circuit device
GB8300732D0 (en) Circuit
EP0151336A3 (en) System for integrated circuit processing
GB8430687D0 (en) Circuit
GB8413349D0 (en) Circuit means
GB2140639B (en) An integrated circuit
EP0120586A3 (en) Signal processing circuits
GB8411891D0 (en) Circuit
GB8422985D0 (en) Circuits
GB8411875D0 (en) Circuits
GB8401298D0 (en) Circuit

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PLESSEY SEMICONDUCTORS LTD., SWINDON, WILTSHIRE, G

8327 Change in the person/name/address of the patent owner

Owner name: MITEL SEMICONDUCTOR LTD., SWINDON, WILTSHIRE, GB