DE3377959D1 - Substrate wiring patterns for mounting integrated-circuit chips - Google Patents

Substrate wiring patterns for mounting integrated-circuit chips

Info

Publication number
DE3377959D1
DE3377959D1 DE8383110496T DE3377959T DE3377959D1 DE 3377959 D1 DE3377959 D1 DE 3377959D1 DE 8383110496 T DE8383110496 T DE 8383110496T DE 3377959 T DE3377959 T DE 3377959T DE 3377959 D1 DE3377959 D1 DE 3377959D1
Authority
DE
Germany
Prior art keywords
wiring patterns
circuit chips
substrate wiring
mounting integrated
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383110496T
Other languages
English (en)
Inventor
Charles Luther Johnson
John Michael Ryba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3377959D1 publication Critical patent/DE3377959D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
DE8383110496T 1982-12-30 1983-10-21 Substrate wiring patterns for mounting integrated-circuit chips Expired DE3377959D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/454,522 US4495377A (en) 1982-12-30 1982-12-30 Substrate wiring patterns for connecting to integrated-circuit chips

Publications (1)

Publication Number Publication Date
DE3377959D1 true DE3377959D1 (en) 1988-10-13

Family

ID=23804949

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383110496T Expired DE3377959D1 (en) 1982-12-30 1983-10-21 Substrate wiring patterns for mounting integrated-circuit chips

Country Status (4)

Country Link
US (1) US4495377A (de)
EP (1) EP0116119B1 (de)
JP (1) JPS59124748A (de)
DE (1) DE3377959D1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5165166A (en) * 1987-09-29 1992-11-24 Microelectronics And Computer Technology Corporation Method of making a customizable circuitry
AU610249B2 (en) * 1987-09-29 1991-05-16 Microelectronics And Computer Technology Corporation Customizable circuitry
US4829405A (en) * 1988-03-14 1989-05-09 International Business Machines Corporation Tape automated bonding package
JPH02173278A (ja) * 1988-12-26 1990-07-04 Hitachi Ltd 微細加工方法及びその装置
FR2647962B1 (fr) * 1989-05-30 1994-04-15 Thomson Composants Milit Spatiau Circuit electronique en boitier avec puce sur zone quadrillee de plots conducteurs
US5068715A (en) * 1990-06-29 1991-11-26 Digital Equipment Corporation High-power, high-performance integrated circuit chip package
JP3389357B2 (ja) * 1994-11-29 2003-03-24 新光電気工業株式会社 半導体チップ搭載用基板
US5784262A (en) * 1995-11-06 1998-07-21 Symbios, Inc. Arrangement of pads and through-holes for semiconductor packages
JP3380151B2 (ja) * 1997-12-22 2003-02-24 新光電気工業株式会社 多層回路基板
JP2000174153A (ja) * 1998-12-01 2000-06-23 Shinko Electric Ind Co Ltd 多層配線基板
US6664620B2 (en) 1999-06-29 2003-12-16 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
JP2001053437A (ja) 1999-08-06 2001-02-23 Shinko Electric Ind Co Ltd 多層回路基板
US6285560B1 (en) * 1999-09-20 2001-09-04 Texas Instruments Incorporated Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
JP3741005B2 (ja) * 2000-09-13 2006-02-01 セイコーエプソン株式会社 配線基板、その製造方法、表示装置および電子機器
US6406936B1 (en) * 2000-12-13 2002-06-18 Lsi Logic Corporation Method for increasing trace rows of a ball grid array
US6664483B2 (en) * 2001-05-15 2003-12-16 Intel Corporation Electronic package with high density interconnect and associated methods
JP3639226B2 (ja) * 2001-07-05 2005-04-20 松下電器産業株式会社 半導体集積回路装置、実装基板および実装体
EP1376698A1 (de) * 2002-06-25 2004-01-02 STMicroelectronics S.r.l. Elektrisch lösch- und programmierbare nicht flüchtige Speicherzelle
US7196908B2 (en) * 2003-06-05 2007-03-27 International Business Machines Corporation Dual pitch contact pad footprint for flip-chip chips and modules
US6793500B1 (en) 2003-09-18 2004-09-21 International Business Machines Corporation Radial contact pad footprint and wiring for electrical components
JP3925503B2 (ja) 2004-03-15 2007-06-06 カシオ計算機株式会社 半導体装置
US20070007323A1 (en) * 2005-07-06 2007-01-11 International Business Machines Corporation Standoff structures for surface mount components
US8053349B2 (en) * 2007-11-01 2011-11-08 Texas Instruments Incorporated BGA package with traces for plating pads under the chip
JP4542587B2 (ja) * 2008-02-04 2010-09-15 日本特殊陶業株式会社 電子部品検査装置用配線基板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716761A (en) * 1972-05-03 1973-02-13 Microsystems Int Ltd Universal interconnection structure for microelectronic devices
US3833838A (en) * 1972-11-13 1974-09-03 A Christiansen Electronic component mounting wafers for repeated connection in a variety of circuit designs
US4195195A (en) * 1978-09-28 1980-03-25 The United States Of America As Represented By The Secretary Of The Army Tape automated bonding test board

Also Published As

Publication number Publication date
EP0116119B1 (de) 1988-09-07
JPS59124748A (ja) 1984-07-18
EP0116119A2 (de) 1984-08-22
JPH0144016B2 (de) 1989-09-25
EP0116119A3 (en) 1985-09-18
US4495377A (en) 1985-01-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee