DE3371442D1 - Method of blowing fuses in an ic, for example for writing information into a fuse-type rom - Google Patents

Method of blowing fuses in an ic, for example for writing information into a fuse-type rom

Info

Publication number
DE3371442D1
DE3371442D1 DE8383307624T DE3371442T DE3371442D1 DE 3371442 D1 DE3371442 D1 DE 3371442D1 DE 8383307624 T DE8383307624 T DE 8383307624T DE 3371442 T DE3371442 T DE 3371442T DE 3371442 D1 DE3371442 D1 DE 3371442D1
Authority
DE
Germany
Prior art keywords
fuse
writing information
type rom
blowing fuses
fuses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383307624T
Other languages
English (en)
Inventor
Ryoichi Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3371442D1 publication Critical patent/DE3371442D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326—Application of electric currents or fields, e.g. for electroforming
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8383307624T 1982-12-25 1983-12-15 Method of blowing fuses in an ic, for example for writing information into a fuse-type rom Expired DE3371442D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226520A JPS59130441A (ja) 1982-12-25 1982-12-25 ヒューズ型ｒｏｍの書込み方法

Publications (1)

Publication Number Publication Date
DE3371442D1 true DE3371442D1 (en) 1987-06-11

Family

ID=16846412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383307624T Expired DE3371442D1 (en) 1982-12-25 1983-12-15 Method of blowing fuses in an ic, for example for writing information into a fuse-type rom

Country Status (4)

Country Link
US (1) US4747076A (de)
EP (1) EP0112693B1 (de)
JP (1) JPS59130441A (de)
DE (1) DE3371442D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679967A (en) * 1985-01-20 1997-10-21 Chip Express (Israel) Ltd. Customizable three metal layer gate array devices
US5545904A (en) * 1986-01-17 1996-08-13 Quick Technologies Ltd. Personalizable gate array devices
JPS6246496A (ja) * 1985-08-23 1987-02-28 Sony Corp 固定記憶装置の書き込み方法
US4792835A (en) * 1986-12-05 1988-12-20 Texas Instruments Incorporated MOS programmable memories using a metal fuse link and process for making the same
US4951098A (en) * 1988-12-21 1990-08-21 Eastman Kodak Company Electrode structure for light emitting diode array chip
JP2695548B2 (ja) * 1991-09-04 1997-12-24 富士通株式会社 半導体装置
EP0563852A1 (de) * 1992-04-02 1993-10-06 Siemens Aktiengesellschaft Zickzack-Schmelzvorrichtung für Anwendungen mit reduziertem Schmelzstrom
US5708291A (en) 1995-09-29 1998-01-13 Intel Corporation Silicide agglomeration fuse device
US6337507B1 (en) * 1995-09-29 2002-01-08 Intel Corporation Silicide agglomeration fuse device with notches to enhance programmability
US7231045B1 (en) * 1999-08-30 2007-06-12 Intel Corporation Secure transaction modem storing unique indicia
US7005727B2 (en) * 2001-12-28 2006-02-28 Intel Corporation Low cost programmable CPU package/substrate
US20040038458A1 (en) * 2002-08-23 2004-02-26 Marr Kenneth W. Semiconductor fuses, semiconductor devices containing the same, and methods of making and using the same
DE10260852B4 (de) * 2002-12-23 2011-05-05 Robert Bosch Gmbh Verfahren zum Abgleichen des elektrischen Widerstands einer Widerstandsbahn
JP4489362B2 (ja) * 2003-03-03 2010-06-23 シャープ株式会社 不揮発性記憶素子、不揮発性記憶回路、不揮発性記憶カードおよび記録再生装置
USRE50035E1 (en) * 2003-03-31 2024-07-09 Sony Group Corporation Semiconductor device
US7417300B2 (en) * 2006-03-09 2008-08-26 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof
US7784009B2 (en) * 2006-03-09 2010-08-24 International Business Machines Corporation Electrically programmable π-shaped fuse structures and design process therefore
US7288804B2 (en) * 2006-03-09 2007-10-30 International Business Machines Corporation Electrically programmable π-shaped fuse structures and methods of fabrication thereof
US7645645B2 (en) * 2006-03-09 2010-01-12 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
US7460003B2 (en) * 2006-03-09 2008-12-02 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
KR20090102555A (ko) * 2008-03-26 2009-09-30 삼성전자주식회사 전기적 퓨즈 소자 및 그 동작방법
US8922328B2 (en) * 2011-08-16 2014-12-30 United Microelectronics Corp. Electrical fuse structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2256688B2 (de) * 1972-11-18 1976-05-06 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zum auftrennen von leiterbahnen auf integrierten schaltkreisen
US4402067A (en) * 1978-02-21 1983-08-30 Moss William E Bidirectional dual port serially controlled programmable read-only memory
JPS5847596Y2 (ja) * 1979-09-05 1983-10-29 富士通株式会社 半導体装置
JPS56156989A (en) * 1980-05-02 1981-12-03 Fujitsu Ltd Semiconductor storage device
US4480318A (en) * 1982-02-18 1984-10-30 Fairchild Camera & Instrument Corp. Method of programming of junction-programmable read-only memories

Also Published As

Publication number Publication date
EP0112693B1 (de) 1987-05-06
EP0112693A1 (de) 1984-07-04
JPS6359252B2 (de) 1988-11-18
JPS59130441A (ja) 1984-07-27
US4747076A (en) 1988-05-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee