DE3369041D1 - Circuit for converting signal levels between a saturated logic and a non-saturated logic - Google Patents

Circuit for converting signal levels between a saturated logic and a non-saturated logic

Info

Publication number
DE3369041D1
DE3369041D1 DE8383201475T DE3369041T DE3369041D1 DE 3369041 D1 DE3369041 D1 DE 3369041D1 DE 8383201475 T DE8383201475 T DE 8383201475T DE 3369041 T DE3369041 T DE 3369041T DE 3369041 D1 DE3369041 D1 DE 3369041D1
Authority
DE
Germany
Prior art keywords
saturated logic
circuit
saturated
logic
signal levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383201475T
Other languages
English (en)
Inventor
Gilbert Gloaguen
Michel Moussie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Radiotechnique Compelec RTC SA
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Radiotechnique Compelec RTC SA, Philips Gloeilampenfabrieken NV filed Critical Radiotechnique Compelec RTC SA
Application granted granted Critical
Publication of DE3369041D1 publication Critical patent/DE3369041D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE8383201475T 1982-10-18 1983-10-14 Circuit for converting signal levels between a saturated logic and a non-saturated logic Expired DE3369041D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8217397A FR2534752A1 (fr) 1982-10-18 1982-10-18 Circuit convertisseur de niveaux de signaux entre une logique de type saturee et une logique de type non saturee

Publications (1)

Publication Number Publication Date
DE3369041D1 true DE3369041D1 (en) 1987-02-12

Family

ID=9278347

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383201475T Expired DE3369041D1 (en) 1982-10-18 1983-10-14 Circuit for converting signal levels between a saturated logic and a non-saturated logic

Country Status (5)

Country Link
US (1) US4612460A (de)
EP (1) EP0109106B1 (de)
JP (1) JPS59103427A (de)
DE (1) DE3369041D1 (de)
FR (1) FR2534752A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0763139B2 (ja) * 1985-10-31 1995-07-05 日本電気株式会社 レベル変換回路
JPH0716154B2 (ja) * 1988-10-06 1995-02-22 日本電気株式会社 Ｔｔｌ−ｅｃｌレベル変換回路
US5059826A (en) * 1989-11-30 1991-10-22 Motorola Inc. Voltage threshold generator for use in diode load emitter coupled logic circuits
US5008570A (en) * 1990-03-30 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Schmitt-triggered TTL to CML input buffer apparatus
DE4201947C2 (de) * 1992-01-24 1993-10-28 Texas Instruments Deutschland Integrierte Transistorschaltung mit Reststromkompensation
US5440248A (en) * 1994-01-31 1995-08-08 Texas Instruments Incorporated Power-saver differential input buffer

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1245347A (en) * 1968-07-01 1971-09-08 Nippon Telegraph & Telephone Improved high speed logic circuit device
DE2000401C3 (de) * 1970-01-07 1974-01-03 Siemens Ag, 1000 Berlin U. 8000 Muenchen Schaltungsanordnung zur Umsetzung von Signalspannungen aus Schaltkreisen mit in der Sättigung betriebenen Transistoren in solche für Schaltkreise, in denen die Sättigung vermieden ist
US3716722A (en) * 1970-04-29 1973-02-13 Cogar Corp Temperature compensation for logic circuits
US3959666A (en) * 1974-07-01 1976-05-25 Honeywell Information Systems, Inc. Logic level translator
US3986045A (en) * 1975-04-23 1976-10-12 Advanced Micro Devices, Inc. High speed logic level converter
JPS56117427A (en) * 1980-02-20 1981-09-14 Fujitsu Ltd Level converting circuit
EP0052565A1 (de) * 1980-11-17 1982-05-26 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Gegen Temperatur- und Herstellungsschwankungen kompensierter TTL-ECL-Verknüpfungspuffer
US4456838A (en) * 1981-02-25 1984-06-26 Tokyo Shibaura Denki Kabushiki Kaisha Level shifting circuit
JPS57162838A (en) * 1981-03-31 1982-10-06 Fujitsu Ltd Emitter coupling type logical circuit
US4518876A (en) * 1983-03-30 1985-05-21 Advanced Micro Devices, Inc. TTL-ECL Input translation with AND/NAND function

Also Published As

Publication number Publication date
JPS59103427A (ja) 1984-06-14
JPH0432571B2 (de) 1992-05-29
US4612460A (en) 1986-09-16
EP0109106B1 (de) 1987-01-07
FR2534752B1 (de) 1984-11-23
EP0109106A1 (de) 1984-05-23
FR2534752A1 (fr) 1984-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee