DE3277482D1 - Method of fabricating a conductive metal silicide structure - Google Patents

Method of fabricating a conductive metal silicide structure

Info

Publication number
DE3277482D1
DE3277482D1 DE8282106251T DE3277482T DE3277482D1 DE 3277482 D1 DE3277482 D1 DE 3277482D1 DE 8282106251 T DE8282106251 T DE 8282106251T DE 3277482 T DE3277482 T DE 3277482T DE 3277482 D1 DE3277482 D1 DE 3277482D1
Authority
DE
Germany
Prior art keywords
fabricating
conductive metal
metal silicide
silicide structure
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282106251T
Other languages
English (en)
Inventor
Henry John Geipel
Larry Alan Nesbit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3277482D1 publication Critical patent/DE3277482D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8282106251T 1981-09-21 1982-07-13 Method of fabricating a conductive metal silicide structure Expired DE3277482D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/304,436 US4398341A (en) 1981-09-21 1981-09-21 Method of fabricating a highly conductive structure

Publications (1)

Publication Number Publication Date
DE3277482D1 true DE3277482D1 (en) 1987-11-19

Family

ID=23176504

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282106251T Expired DE3277482D1 (en) 1981-09-21 1982-07-13 Method of fabricating a conductive metal silicide structure

Country Status (4)

Country Link
US (1) US4398341A (de)
EP (1) EP0075085B1 (de)
JP (1) JPS5863174A (de)
DE (1) DE3277482D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495512A (en) * 1982-06-07 1985-01-22 International Business Machines Corporation Self-aligned bipolar transistor with inverted polycide base contact
US4470189A (en) * 1983-05-23 1984-09-11 International Business Machines Corporation Process for making polycide structures
US4453306A (en) * 1983-05-27 1984-06-12 At&T Bell Laboratories Fabrication of FETs
JPS6037124A (ja) * 1983-08-09 1985-02-26 Seiko Epson Corp 半導体装置
US4609429A (en) * 1984-07-02 1986-09-02 International Business Machines Corporation Process for making a small dynamic memory cell structure
FR2571177B1 (fr) * 1984-10-02 1987-02-27 Thomson Csf Procede de realisation de grilles en siliciure ou en silicium pour circuit integre comportant des elements du type grille - isolant - semi-conducteur
US4660276A (en) * 1985-08-12 1987-04-28 Rca Corporation Method of making a MOS field effect transistor in an integrated circuit
US4751198A (en) * 1985-09-11 1988-06-14 Texas Instruments Incorporated Process for making contacts and interconnections using direct-reacted silicide
US4970573A (en) * 1986-07-01 1990-11-13 Harris Corporation Self-planarized gold interconnect layer
GB8710359D0 (en) * 1987-05-01 1987-06-03 Inmos Ltd Semiconductor element
US4771017A (en) * 1987-06-23 1988-09-13 Spire Corporation Patterning process
US4902379A (en) * 1988-02-08 1990-02-20 Eastman Kodak Company UHV compatible lift-off method for patterning nobel metal silicide
US5010037A (en) * 1988-10-14 1991-04-23 California Institute Of Technology Pinhole-free growth of epitaxial CoSi2 film on Si(111)
JPH02141569A (ja) * 1988-11-24 1990-05-30 Hitachi Ltd 超伝導材料
EP0388563B1 (de) * 1989-03-24 1994-12-14 STMicroelectronics, Inc. Verfahren zum Herstellen eines Kontaktes/VIA
US5106786A (en) * 1989-10-23 1992-04-21 At&T Bell Laboratories Thin coatings for use in semiconductor integrated circuits and processes as antireflection coatings consisting of tungsten silicide
EP0499855A3 (en) * 1991-02-21 1992-10-28 Texas Instruments Incorporated Method and structure for microelectronic device incorporating low-resistivity straps between conductive regions
JPH05198739A (ja) * 1991-09-10 1993-08-06 Mitsubishi Electric Corp 積層型半導体装置およびその製造方法
US5401677A (en) * 1993-12-23 1995-03-28 International Business Machines Corporation Method of metal silicide formation in integrated circuit devices
JP2950232B2 (ja) * 1996-03-29 1999-09-20 日本電気株式会社 半導体記憶装置の製造方法
IT1285146B1 (it) * 1996-05-31 1998-06-03 Texas Instruments Italia Spa Procedimento per la realizzazione di configurazioni di polisilicio drogato in transistori mos.
JP3209164B2 (ja) * 1997-10-07 2001-09-17 日本電気株式会社 半導体装置の製造方法
US6524937B1 (en) * 2000-08-23 2003-02-25 Tyco Electronics Corp. Selective T-gate process
CN117542733B (zh) * 2024-01-10 2024-04-26 合肥晶合集成电路股份有限公司 半导体结构的制作方法、电路及芯片

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617824A (en) * 1965-07-12 1971-11-02 Nippon Electric Co Mos device with a metal-silicide gate
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
US4263058A (en) * 1979-06-11 1981-04-21 General Electric Company Composite conductive structures in integrated circuits and method of making same
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices

Also Published As

Publication number Publication date
JPS626351B2 (de) 1987-02-10
JPS5863174A (ja) 1983-04-14
EP0075085A2 (de) 1983-03-30
EP0075085B1 (de) 1987-10-14
US4398341A (en) 1983-08-16
EP0075085A3 (en) 1985-01-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee