DE3175339D1 - Single polycrystalline silicon static fet flip flop memory cell - Google Patents

Single polycrystalline silicon static fet flip flop memory cell

Info

Publication number
DE3175339D1
DE3175339D1 DE8181302869T DE3175339T DE3175339D1 DE 3175339 D1 DE3175339 D1 DE 3175339D1 DE 8181302869 T DE8181302869 T DE 8181302869T DE 3175339 T DE3175339 T DE 3175339T DE 3175339 D1 DE3175339 D1 DE 3175339D1
Authority
DE
Germany
Prior art keywords
memory cell
polycrystalline silicon
flip flop
single polycrystalline
flop memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181302869T
Other languages
English (en)
Inventor
Kim Carver Hardee
Rahul Sud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inmos Corp
Original Assignee
Inmos Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inmos Corp filed Critical Inmos Corp
Application granted granted Critical
Publication of DE3175339D1 publication Critical patent/DE3175339D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8181302869T 1980-06-30 1981-06-25 Single polycrystalline silicon static fet flip flop memory cell Expired DE3175339D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/164,285 US4471374A (en) 1980-06-30 1980-06-30 Single polycrystalline silicon memory cell

Publications (1)

Publication Number Publication Date
DE3175339D1 true DE3175339D1 (en) 1986-10-23

Family

ID=22593804

Family Applications (2)

Application Number Title Priority Date Filing Date
DE8181302869T Expired DE3175339D1 (en) 1980-06-30 1981-06-25 Single polycrystalline silicon static fet flip flop memory cell
DE198181302869T Pending DE43244T1 (de) 1980-06-30 1981-06-25 Statische fet-flip-flop-speicherzelle mit einer einzigen polykristallinen siliziumschicht.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE198181302869T Pending DE43244T1 (de) 1980-06-30 1981-06-25 Statische fet-flip-flop-speicherzelle mit einer einzigen polykristallinen siliziumschicht.

Country Status (5)

Country Link
US (1) US4471374A (de)
EP (1) EP0043244B1 (de)
JP (1) JPS5773968A (de)
CA (1) CA1149950A (de)
DE (2) DE3175339D1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3380548D1 (en) * 1982-03-03 1989-10-12 Fujitsu Ltd A semiconductor memory device
US4554644A (en) * 1982-06-21 1985-11-19 Fairchild Camera & Instrument Corporation Static RAM cell
JPS59155165A (ja) * 1983-02-23 1984-09-04 Toshiba Corp 半導体記憶装置
JPS604253A (ja) * 1983-06-23 1985-01-10 Nec Corp 半導体集積回路メモリ
DE3330026A1 (de) * 1983-08-19 1985-02-28 Siemens AG, 1000 Berlin und 8000 München Integrierte rs-flipflop-schaltung
DE3330013A1 (de) * 1983-08-19 1985-02-28 Siemens AG, 1000 Berlin und 8000 München Statische speicherzelle
US4847732A (en) * 1983-09-15 1989-07-11 Mosaic Systems, Inc. Wafer and method of making same
EP0464866A3 (en) * 1984-02-21 1992-07-15 Mosaic Systems, Inc. Wafer and method of making same
JPS60206161A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体集積回路
US5202751A (en) * 1984-03-30 1993-04-13 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
KR940002772B1 (ko) * 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치 및 그 제조방법
JPH0652782B2 (ja) * 1984-08-31 1994-07-06 株式会社日立製作所 半導体集積回路装置
JPS63500555A (ja) * 1985-07-29 1988-02-25 アメリカン テレフオン アンド テレグラフ カムパニ− 集積回路のための３レベル相互接続法
JPH0746702B2 (ja) * 1986-08-01 1995-05-17 株式会社日立製作所 半導体記憶装置
GB8700347D0 (en) * 1987-01-08 1987-02-11 Inmos Ltd Memory cell
US4920388A (en) * 1987-02-17 1990-04-24 Siliconix Incorporated Power transistor with integrated gate resistor
JPH061822B2 (ja) * 1989-05-24 1994-01-05 株式会社日立製作所 半導体集積回路装置の製法
US5838044A (en) * 1995-12-12 1998-11-17 Advanced Micro Devices Integrated circuit having improved polysilicon resistor structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4208781A (en) * 1976-09-27 1980-06-24 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4110776A (en) * 1976-09-27 1978-08-29 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
JPS5828744B2 (ja) * 1977-05-31 1983-06-17 テキサス インスツルメンツ インコ−ポレイテツド シリコンゲ−ト型集積回路デバイスおよびその製造方法
US4240097A (en) * 1977-05-31 1980-12-16 Texas Instruments Incorporated Field-effect transistor structure in multilevel polycrystalline silicon
US4246593A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell with polysilicon resistors
US4280271A (en) * 1979-10-11 1981-07-28 Texas Instruments Incorporated Three level interconnect process for manufacture of integrated circuit devices
US4322824A (en) * 1979-11-13 1982-03-30 Texas Instruments Incorporated Static random access memory with merged bit lines

Also Published As

Publication number Publication date
EP0043244A2 (de) 1982-01-06
CA1149950A (en) 1983-07-12
JPH031837B2 (de) 1991-01-11
US4471374A (en) 1984-09-11
DE43244T1 (de) 1986-02-27
JPS5773968A (en) 1982-05-08
EP0043244A3 (en) 1983-07-20
EP0043244B1 (de) 1986-09-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition