DE3173316D1 - Method of manufacturing semiconductor devices using self-alignment techniques - Google Patents

Method of manufacturing semiconductor devices using self-alignment techniques

Info

Publication number
DE3173316D1
DE3173316D1 DE8181107436T DE3173316T DE3173316D1 DE 3173316 D1 DE3173316 D1 DE 3173316D1 DE 8181107436 T DE8181107436 T DE 8181107436T DE 3173316 T DE3173316 T DE 3173316T DE 3173316 D1 DE3173316 D1 DE 3173316D1
Authority
DE
Germany
Prior art keywords
self
semiconductor devices
manufacturing semiconductor
alignment techniques
alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181107436T
Other languages
German (de)
English (en)
Inventor
Mamoru Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3173316D1 publication Critical patent/DE3173316D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34—Bipolar devices
    • H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/092—Laser beam processing-diodes or transistor
DE8181107436T 1980-09-26 1981-09-18 Method of manufacturing semiconductor devices using self-alignment techniques Expired DE3173316D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55132850A JPS5758356A (en) 1980-09-26 1980-09-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
DE3173316D1 true DE3173316D1 (en) 1986-02-06

Family

ID=15090975

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181107436T Expired DE3173316D1 (en) 1980-09-26 1981-09-18 Method of manufacturing semiconductor devices using self-alignment techniques

Country Status (4)

Country Link
US (1) US4398962A (https=)
EP (1) EP0052198B1 (https=)
JP (1) JPS5758356A (https=)
DE (1) DE3173316D1 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752817A (en) * 1983-08-26 1988-06-21 International Business Machines Corporation High performance integrated circuit having modified extrinsic base
JPS60258964A (ja) * 1984-06-06 1985-12-20 Hitachi Ltd 半導体装置の製造方法
US5098854A (en) * 1984-07-09 1992-03-24 National Semiconductor Corporation Process for forming self-aligned silicide base contact for bipolar transistor
US5227316A (en) * 1985-01-22 1993-07-13 National Semiconductor Corporation Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size
GB2188479B (en) * 1986-03-26 1990-05-23 Stc Plc Semiconductor devices
JPS62290173A (ja) * 1986-06-09 1987-12-17 Oki Electric Ind Co Ltd 半導体集積回路装置の製造方法
US4974046A (en) * 1986-07-02 1990-11-27 National Seimconductor Corporation Bipolar transistor with polysilicon stringer base contact
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
JPS63182860A (ja) * 1987-01-26 1988-07-28 Toshiba Corp 半導体装置とその製造方法
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
US4857476A (en) * 1988-01-26 1989-08-15 Hewlett-Packard Company Bipolar transistor process using sidewall spacer for aligning base insert
US5064773A (en) * 1988-12-27 1991-11-12 Raytheon Company Method of forming bipolar transistor having closely spaced device regions
US4992134A (en) * 1989-11-14 1991-02-12 Advanced Micro Devices, Inc. Dopant-independent polysilicon plasma etch
JP3333560B2 (ja) * 1992-10-23 2002-10-15 リコーエレメックス株式会社 シリコン基板のエッチング方法
US6136656A (en) * 1998-10-22 2000-10-24 International Business Machines Corporation Method to create a depleted poly MOSFET
US8791546B2 (en) * 2010-10-21 2014-07-29 Freescale Semiconductor, Inc. Bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations
US9099489B2 (en) 2012-07-10 2015-08-04 Freescale Semiconductor Inc. Bipolar transistor with high breakdown voltage
US9054149B2 (en) * 2012-09-06 2015-06-09 Freescale Semiconductor, Inc. Semiconductor device with diagonal conduction path

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753807A (en) * 1972-02-24 1973-08-21 Bell Canada Northern Electric Manufacture of bipolar semiconductor devices
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
JPS51130174A (en) * 1975-05-06 1976-11-12 Matsushita Electric Ind Co Ltd Semiconductor device process
JPS5221774A (en) * 1975-08-12 1977-02-18 Nippon Telegr & Teleph Corp <Ntt> Producing system for transistor
JPS6022506B2 (ja) * 1977-01-24 1985-06-03 日本電気株式会社 半導体装置の製法
NL7703941A (nl) * 1977-04-12 1978-10-16 Philips Nv Werkwijze ter vervaardiging van een halfgelei- derinrichting en inrichting, vervaardigd door toepassing van de werkwijze.
JPS5467778A (en) * 1977-11-10 1979-05-31 Toshiba Corp Production of semiconductor device
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
JPS5512754A (en) * 1978-07-13 1980-01-29 Nec Corp Semiconductor device manufacturing method
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
JPS5586151A (en) * 1978-12-23 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor integrated circuit
US4243435A (en) * 1979-06-22 1981-01-06 International Business Machines Corporation Bipolar transistor fabrication process with an ion implanted emitter
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor

Also Published As

Publication number Publication date
JPS5758356A (en) 1982-04-08
EP0052198A2 (en) 1982-05-26
EP0052198B1 (en) 1985-12-27
EP0052198A3 (en) 1983-06-29
JPH0340501B2 (https=) 1991-06-19
US4398962A (en) 1983-08-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee