DE3148957C2 - Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben - Google Patents

Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben

Info

Publication number
DE3148957C2
DE3148957C2 DE3148957A DE3148957A DE3148957C2 DE 3148957 C2 DE3148957 C2 DE 3148957C2 DE 3148957 A DE3148957 A DE 3148957A DE 3148957 A DE3148957 A DE 3148957A DE 3148957 C2 DE3148957 C2 DE 3148957C2
Authority
DE
Germany
Prior art keywords
semiconductor wafers
abrasive grain
wafers
roller
rollers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3148957A
Other languages
German (de)
English (en)
Other versions
DE3148957A1 (de
Inventor
Walter Ing.(grad.) 8263 Burghausen Auer
Alfred Pischelsdorf Buchner
Franz Kuhn Dr. Dipl.-Phys. 8261 Emmerting Kuhnenfeld
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Wacker Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wacker Siltronic AG filed Critical Wacker Siltronic AG
Priority to DE3148957A priority Critical patent/DE3148957C2/de
Priority to JP57141754A priority patent/JPS58102529A/ja
Priority to US06/421,452 priority patent/US4587771A/en
Priority to IT49316/82A priority patent/IT1157228B/it
Publication of DE3148957A1 publication Critical patent/DE3148957A1/de
Application granted granted Critical
Publication of DE3148957C2 publication Critical patent/DE3148957C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE3148957A 1981-12-10 1981-12-10 Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben Expired DE3148957C2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE3148957A DE3148957C2 (de) 1981-12-10 1981-12-10 Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben
JP57141754A JPS58102529A (ja) 1981-12-10 1982-08-17 半導体デイスクの背面ゲツタ−リング表面処理方法
US06/421,452 US4587771A (en) 1981-12-10 1982-09-22 Process for the backside-gettering surface treatment of semiconductor wafers
IT49316/82A IT1157228B (it) 1981-12-10 1982-10-20 Procedimento per il trattamento superficiale getterizzante il lato dorsale di piatrine di semiconduttori

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3148957A DE3148957C2 (de) 1981-12-10 1981-12-10 Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben

Publications (2)

Publication Number Publication Date
DE3148957A1 DE3148957A1 (de) 1983-06-23
DE3148957C2 true DE3148957C2 (de) 1987-01-02

Family

ID=6148400

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3148957A Expired DE3148957C2 (de) 1981-12-10 1981-12-10 Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben

Country Status (4)

Country Link
US (1) US4587771A ( )
JP (1) JPS58102529A ( )
DE (1) DE3148957C2 ( )
IT (1) IT1157228B ( )

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6064436A (ja) * 1983-09-19 1985-04-13 Fujitsu Ltd スピンドライヤ
DE3738344A1 (de) * 1986-11-14 1988-05-26 Mitsubishi Electric Corp Anlage zum einfuehren von gitterstoerstellen und verfahren dazu
DE3737815A1 (de) * 1987-11-06 1989-05-18 Wacker Chemitronic Siliciumscheiben zur erzeugung von oxidschichten hoher durchschlagsfestigkeit und verfahren zur ihrer herstellung
DE3934140A1 (de) * 1989-10-12 1991-04-18 Wacker Chemitronic Verfahren zur die ausbildung von getterfaehigen zentren induzierenden oberflaechenbehandlung von halbleiterscheiben und dadurch erhaeltliche beidseitig polierte scheiben
JP2610703B2 (ja) * 1990-09-05 1997-05-14 住友電気工業株式会社 半導体素子の製造方法
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices
US5679059A (en) * 1994-11-29 1997-10-21 Ebara Corporation Polishing aparatus and method
JP2719113B2 (ja) * 1994-05-24 1998-02-25 信越半導体株式会社 単結晶シリコンウェーハの歪付け方法
US5731243A (en) * 1995-09-05 1998-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cleaning residue on a semiconductor wafer bonding pad
DE19534080A1 (de) * 1995-09-14 1997-03-20 Wacker Siltronic Halbleitermat Verfahren zur Erzeugung einer stapelfehlerinduzierenden Beschädigung auf der Rückseite von Halbleiterscheiben
US5766061A (en) * 1996-10-04 1998-06-16 Eco-Snow Systems, Inc. Wafer cassette cleaning using carbon dioxide jet spray
US5938508A (en) * 1997-08-11 1999-08-17 Micron Electronics, Inc. Method for removing marks from integrated circuit devices and devices so processed
US5997388A (en) * 1997-08-11 1999-12-07 Micron Electronics, Inc. Apparatus for removing marks from integrated circuit devices
US6184064B1 (en) 2000-01-12 2001-02-06 Micron Technology, Inc. Semiconductor die back side surface and method of fabrication
KR20030012332A (ko) * 2001-07-31 2003-02-12 오일광 드럼형 가공휠을 이용한 평면 자동연마장치
US6879050B2 (en) * 2003-02-11 2005-04-12 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
US10283595B2 (en) * 2015-04-10 2019-05-07 Panasonic Corporation Silicon carbide semiconductor substrate used to form semiconductor epitaxial layer thereon

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3905162A (en) * 1974-07-23 1975-09-16 Silicon Material Inc Method of preparing high yield semiconductor wafer
DE2537464A1 (de) * 1975-08-22 1977-03-03 Wacker Chemitronic Verfahren zur entfernung spezifischer kristallbaufehler aus halbleiterscheiben
JPS5378170A (en) * 1976-12-22 1978-07-11 Toshiba Corp Continuous processor for gas plasma etching
JPS54110783A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Semiconductor substrate and its manufacture
DE2909470A1 (de) * 1979-03-10 1980-09-11 Walter Krepcke Betonbauelement zur errichtung von winkelstuetzmauern
DE2927220A1 (de) * 1979-07-05 1981-01-15 Wacker Chemitronic Verfahren zur stapelfehlerinduzierenden oberflaechenzerstoerung von halbleiterscheiben

Also Published As

Publication number Publication date
US4587771A (en) 1986-05-13
JPS58102529A (ja) 1983-06-18
DE3148957A1 (de) 1983-06-23
IT8249316A0 (it) 1982-10-20
IT1157228B (it) 1987-02-11

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee