DE2744531C2 - Anordnung zur Auswahl von Unterbrechnungsprogrammen in einer Datenverarbeitungsanlage - Google Patents

Anordnung zur Auswahl von Unterbrechnungsprogrammen in einer Datenverarbeitungsanlage

Info

Publication number
DE2744531C2
DE2744531C2 DE2744531A DE2744531A DE2744531C2 DE 2744531 C2 DE2744531 C2 DE 2744531C2 DE 2744531 A DE2744531 A DE 2744531A DE 2744531 A DE2744531 A DE 2744531A DE 2744531 C2 DE2744531 C2 DE 2744531C2
Authority
DE
Germany
Prior art keywords
interrupt
dma
cycle
signal
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2744531A
Other languages
German (de)
English (en)
Other versions
DE2744531A1 (de
Inventor
Paul Michael Princeton N.J. Russo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE2744531A1 publication Critical patent/DE2744531A1/de
Application granted granted Critical
Publication of DE2744531C2 publication Critical patent/DE2744531C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
DE2744531A 1976-10-04 1977-10-04 Anordnung zur Auswahl von Unterbrechnungsprogrammen in einer Datenverarbeitungsanlage Expired DE2744531C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/729,348 US4090238A (en) 1976-10-04 1976-10-04 Priority vectored interrupt using direct memory access

Publications (2)

Publication Number Publication Date
DE2744531A1 DE2744531A1 (de) 1978-04-06
DE2744531C2 true DE2744531C2 (de) 1985-02-07

Family

ID=24930639

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2744531A Expired DE2744531C2 (de) 1976-10-04 1977-10-04 Anordnung zur Auswahl von Unterbrechnungsprogrammen in einer Datenverarbeitungsanlage

Country Status (6)

Country Link
US (1) US4090238A (Direct)
JP (1) JPS5355924A (Direct)
DE (1) DE2744531C2 (Direct)
FR (1) FR2366627A1 (Direct)
GB (1) GB1588929A (Direct)
IT (1) IT1087551B (Direct)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3715291A1 (de) * 1987-05-08 1988-11-24 Telefonbau & Normalzeit Gmbh Schaltungsanordnung zur erweiterung der anschlussmoeglichkeiten fuer mit einer zentralen steuereinrichtung zusammenarbeitende periphere einheiten

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US4271466A (en) * 1975-02-20 1981-06-02 Panafacom Limited Direct memory access control system with byte/word control of data bus
US4315314A (en) * 1977-12-30 1982-02-09 Rca Corporation Priority vectored interrupt having means to supply branch address directly
IT1192603B (it) * 1977-12-30 1988-04-20 Rca Corp Apparato di interruzione di un programma,su base prioritaria,dotato di mezzi per l'alimentazione diretta dell'indirizzo di salto
US4403282A (en) * 1978-01-23 1983-09-06 Data General Corporation Data processing system using a high speed data channel for providing direct memory access for block data transfers
US4200912A (en) * 1978-07-31 1980-04-29 Motorola, Inc. Processor interrupt system
GB2076192B (en) * 1978-12-26 1983-06-02 Honeywell Inf Systems Improvements in or relating to terminal systems for data processors
US4240140A (en) * 1978-12-26 1980-12-16 Honeywell Information Systems Inc. CRT display terminal priority interrupt apparatus for generating vectored addresses
US4237535A (en) * 1979-04-11 1980-12-02 Sperry Rand Corporation Apparatus and method for receiving and servicing request signals from peripheral devices in a data processing system
US4310880A (en) * 1979-09-10 1982-01-12 Nixdorf Computer Corporation High-speed synchronous computer using pipelined registers and a two-level fixed priority circuit
FR2465269B1 (fr) * 1979-09-12 1985-12-27 Cii Honeywell Bull Selecteur de demandes asynchrones dans un systeme de traitement de l'information
DE3003340C2 (de) * 1980-01-30 1985-08-22 Siemens AG, 1000 Berlin und 8000 München Verfahren und Schaltungsanordnung zur Übertragung von binären Signalen zwischen über ein zentrales Busleitungssystem miteinander verbundenen Anschlußgeräten
IT1145730B (it) * 1981-11-13 1986-11-05 Olivetti & Co Spa Sistema di elaborazione di dati con dispositivo di controllo delle interruzioni di programma
DE3233542A1 (de) * 1982-09-10 1984-03-15 Philips Kommunikations Industrie AG, 8500 Nürnberg Verfahren und schaltungsanordnung zur abgabe von unterbrechungs-anforderungssignalen
US4523277A (en) * 1982-09-30 1985-06-11 Ncr Corporation Priority interrupt system for microcomputer
US4807117A (en) * 1983-07-19 1989-02-21 Nec Corporation Interruption control apparatus
US4627018A (en) * 1983-09-08 1986-12-02 Sperry Corporation Priority requestor accelerator
US4631670A (en) * 1984-07-11 1986-12-23 Ibm Corporation Interrupt level sharing
US4964034A (en) * 1984-10-30 1990-10-16 Raytheon Company Synchronized processing system with bus arbiter which samples and stores bus request signals and synchronizes bus grant signals according to clock signals
US4908749A (en) * 1985-11-15 1990-03-13 Data General Corporation System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal
JPS62226257A (ja) * 1986-03-27 1987-10-05 Toshiba Corp 演算処理装置
US4961067A (en) * 1986-07-28 1990-10-02 Motorola, Inc. Pattern driven interrupt in a digital data processor
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
US5179696A (en) * 1987-07-24 1993-01-12 Nec Corporation Generator detecting internal and external ready signals for generating a bus cycle end signal for microprocessor debugging operation
JPH01180626A (ja) * 1988-01-12 1989-07-18 Mitsubishi Electric Corp 優先順位分解器
JPH02224140A (ja) * 1989-02-27 1990-09-06 Nippon Motoroola Kk 割込試験装置
US5276818A (en) * 1989-04-24 1994-01-04 Hitachi, Ltd. Bus system for information processing system and method of controlling the same
EP0464237A1 (en) * 1990-07-03 1992-01-08 International Business Machines Corporation Bus arbitration scheme
CA2145553C (en) * 1994-03-30 1999-12-21 Yuuki Date Multi-processor system including priority arbitrator for arbitrating request issued from processors
US6374320B1 (en) 1998-08-10 2002-04-16 Micron Technology, Inc Method for operating core logic unit with internal register for peripheral status
US6189049B1 (en) * 1998-08-10 2001-02-13 Micron Technology Method for operating processor with internal register for peripheral status
US6219720B1 (en) 1998-08-10 2001-04-17 Micron Technology, Inc. Core logic unit with internal register for peripheral status
US6233627B1 (en) 1998-08-10 2001-05-15 Micron Technology, Inc. Processor with internal register for peripheral status
DE69937985T2 (de) * 1998-10-27 2008-12-24 Canon K.K. Bildverarbeitungsvorrichtung und -Verfahren
US8094677B2 (en) * 2007-02-27 2012-01-10 Integrated Device Technology, Inc. Multi-bus structure for optimizing system performance of a serial buffer
US20080209089A1 (en) * 2007-02-27 2008-08-28 Integrated Device Technology, Inc. Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor Port
US7870313B2 (en) * 2007-02-27 2011-01-11 Integrated Device Technology, Inc. Method and structure to support system resource access of a serial device implementating a lite-weight protocol
US7617346B2 (en) * 2007-02-27 2009-11-10 Integrated Device Technology, Inc. Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency
US8516163B2 (en) * 2007-02-27 2013-08-20 Integrated Device Technology, Inc. Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1232587A (fr) * 1959-06-24 1960-10-10 Bull Sa Machines Perfectionnements aux dispositifs d'organisation interne et de coordination des transferts d'informations dans une machine calculatrice électronique
US3665415A (en) * 1970-04-29 1972-05-23 Honeywell Inf Systems Data processing system with program interrupt priority apparatus utilizing working store for multiplexing interrupt requests
GB1397438A (en) * 1971-10-27 1975-06-11 Ibm Data processing system
US3800287A (en) * 1972-06-27 1974-03-26 Honeywell Inf Systems Data processing system having automatic interrupt identification technique
JPS5242498B2 (Direct) * 1972-08-19 1977-10-25
US3766526A (en) * 1972-10-10 1973-10-16 Atomic Energy Commission Multi-microprogrammed input-output processor
US3833888A (en) * 1973-02-05 1974-09-03 Honeywell Inf Systems General purpose digital processor for terminal devices
US3815105A (en) * 1973-09-26 1974-06-04 Corning Glass Works Priority interrupt system
US3944985A (en) * 1973-10-19 1976-03-16 Texas Instruments Incorporated Workspace addressing system
US3943495A (en) * 1973-12-26 1976-03-09 Xerox Corporation Microprocessor with immediate and indirect addressing
JPS50106541A (Direct) * 1974-01-29 1975-08-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3715291A1 (de) * 1987-05-08 1988-11-24 Telefonbau & Normalzeit Gmbh Schaltungsanordnung zur erweiterung der anschlussmoeglichkeiten fuer mit einer zentralen steuereinrichtung zusammenarbeitende periphere einheiten

Also Published As

Publication number Publication date
IT1087551B (it) 1985-06-04
JPS5732817B2 (Direct) 1982-07-13
US4090238A (en) 1978-05-16
DE2744531A1 (de) 1978-04-06
FR2366627A1 (fr) 1978-04-28
FR2366627B1 (Direct) 1981-12-04
GB1588929A (en) 1981-04-29
JPS5355924A (en) 1978-05-20

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee