DE2620707B2 - Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung - Google Patents

Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung

Info

Publication number
DE2620707B2
DE2620707B2 DE2620707A DE2620707A DE2620707B2 DE 2620707 B2 DE2620707 B2 DE 2620707B2 DE 2620707 A DE2620707 A DE 2620707A DE 2620707 A DE2620707 A DE 2620707A DE 2620707 B2 DE2620707 B2 DE 2620707B2
Authority
DE
Germany
Prior art keywords
semiconductor circuit
coating
producing
tubes
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE2620707A
Other languages
English (en)
Other versions
DE2620707A1 (de
DE2620707C3 (de
Inventor
Tuh-Kai Colorado Springs Col. Koo
Armand Joseph Antoine Van West Carrollton Ohio Velthoven
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of DE2620707A1 publication Critical patent/DE2620707A1/de
Publication of DE2620707B2 publication Critical patent/DE2620707B2/de
Application granted granted Critical
Publication of DE2620707C3 publication Critical patent/DE2620707C3/de
Expired legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • C23C16/042Coating on selected surface areas, e.g. using masks using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • H01L21/31612Deposition of SiO2 on a silicon body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

Die Erfindung betrifft eine Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung mit einer Maskenanordnung zum Abdecken von nicht zu beschichtenden Bereichen.
Allgemein bekannte Verfahren zur Erzeugung von Überzügen enthalten häufig einen Herstellungsschritt, bei dem eine Halbleitervorrichtung in einer gasförmigen Atmosphäre aufgeheizt wird, um eine Schicht aus festem anorganischen Material, z. B. aus Siliciumdioxid oder Siliciumnitrid, auf der Oberfläche einer Halbleitervorrichtung aufzubringen. Dies geschieht entweder durch Reaktion des Gases mit der Materialoberfläche (Silicium) oder durch Reaktion zweier Komponenten eines Gasgemisches, z. B. aus Silan und Sauerstoff, auf der beheizten Oberfläche.
Aus der Zeitschrift »Elektronik«, 17. Jahrgang (1968), Heft 5, Seiten 143 bis 146 ist es bereits bekannt, bewegliche Masken auf Substraten anzuordnen, die auf bestimmten Bereichen mit Beschichtungen versehen werden sollen. Diese Masken weisen den Nachteil auf, daß zusätzliche Mittel und Geräte zum Abtransport von gasförmigen Substanzen erforderlich sind.
Es ist deshalb die Aufgabe der Erfindung, eine Vorrichtung aufzuzeigen, mit der auf einfache und exakte Weise eine Beschichtung ausgewählter Bereiche möglich ist und die gleichzeitig Mittel zum Absaugen von Gasen aufweist.
Diese Aufgabe wird dadurch gelöst, daß die Maskenanordnung aus zwei im Abstand ineinanderliegende Röhren besteht, von denen die eine, innere Röhre in der anderen, äußeren Röhre angeordnet ist, wobei die innere Röhre der Zuführung der gasförmigen Atmosphäre, die äußere, auf die Oberfläche der integrierten Halbleiterschaltung aufzusetzende Röhre der Abdekkung der nicht zu beschichtenden Bereiche und der
Raum zwischen den Röhren der Abführung der gasförmigen Atmosphäre dient.
Im folgenden wird ein erfindungsgemäßes Ausführungsbeispiel beschrieben, wobei auf die Zeichnung Bezug genommen wird.
Die Zeichnung nach der Figur zeigt im Schnitt eine vergrößerte Darstellung eines Teils einer Halbleiterschaltung und einer Maskenanordnung.
Auf einer Heizplatte 10 in der Figur ist eine Halbleiterschaltung 11 angeordnet, die Chips 14 und 15 enthält. Die Chips 14 und 15 sind jeweils auf einem Trägersubstratbereich 17 und 18 angeordnet Mit den Chips 14 und 15 sind elektrische Zuleitungen in Form von Leiterbahnen 32,37,42 und 47 über Leitungsdrähte 94, 98, 100, 101 und 95, 99, 102, 103 verbunden. Die Vorrichtung enthält Gaszuführungs- und -ableitungsröhren, die jeweils allgemein mit 85 und 86 bezeichnet werden, und die jeweils über einem der Chips 14 bzw. 15 angeordnet sind. Die Gaszuführungs- und -ableitungsröhren 85 bestehen aus einer äußeren Röhre 90, die ein erweitertes Ende 92 aufweist, das über die ausgewählten, mit einem Überzug zu versehenen Teile, aufgesetzt ist Eine innere, konzentrisch in der äußeren Röhre 90 angeordnete Röhre 96 ist von der äußeren Röhre 90 beabstandet, so daß zwischen den beiden Röhren 90 und 96 ein Abführungsweg für die gasförmige Atmosphäre entsteht Ähnlich sind die Gaszuführungs- und -ableitungsröhren 86 angeordnet, die aus einer äußeren Röhre 91 mit einem erweiterten Ende 93 und einer in dieser konzentrisch angeordneten inneren Röhre 97 bestehen.
Die Gaszuführungs- und -ableitungsröhren 86 sind mit; dem erweiteren Ende 93 auf einen ausgewählten Bereich der Halbleiterschaltung 11 aufgesetzt.
Nachdem jeweils die Halbleiterschaltung 11 auf der Heizplatte 10 und die Gaszuführungs- und -ableitungsröhren 85 und 86 über den Chips 14 und 15 positioniert sind, wird die gesamte Anordnung auf mindestens 35O0C erhitzt und anschließend eine Mischung aus Sauerstoff, Silan und einem Trägergas, z. B. Stickstoff, durch die inneren Röhren 96 und 97 auf die ausgewählten Bereiche, die durch die Enden 92 und 93 abgedeckt sind, geleitet. Schichten aus Siliciumdioxid 98 und 99 werden dann über den Chips 14 und 15 und über den entsprechenden diesen zugeordneten Verbindungsdräh-
ten abgelagert. Die Dicke der Siliciumdioxidschicht beträgt etwa 1 μίτι. Das abgesaugte Gas einschließlich anderer Produkte, die durch die chemische Ablagerung der Siliciumdioxidschicht entstanden, werden durch den zwischen den inneren Röhren 96 bzw. 97 und den äußeren Röhren 90 bzw. 91 gebildeten Raum abgesaugt. Die Enden 92 und 93 dienen zur Abdeckung jener Bereiche der Vorrichtung, die außerhalb der nicht zu beschichtenden Bereiche liegen, so daß das Gasgemisch nur auf die ausgewählten Bereiche gelangt und somit verhindert wird, daß unerwünschte Beschichtungen entstehen. Eine Kühlvorrichtung 105 ist um die äußere Röhre 90 und eine Kühlvorrichtung 106 um die äußere Röhre 91 zur Kühlung des abgesaugten Gases angeordnet Diese Kühlvorrichtungen 105 und 106 können jeweils aus schraubenförmiggewundenen Kühlröhren bestehen.
Hierzu 1 Blatt Zeichnungen

Claims (2)

Patentansprüche:
1. Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung mit einer Maskenanordnung zum Abdecken von nicht zu beschichtenden Bereichen, dadurch gekennzeichnet, daß die Maskenanordnung aus zwei mit Abstand ineinanderliegenden Röhren (90,91,96, 97) besteht, von denen die eine, innere Röhre (96,97) in der anderen, äußeren Röhre (90, 91) angeordnet ist, wobei die innere Röhre (96, 97) der Zuführung der gasförmigen Atmosphäre, die äußere, auf die Oberfläche der integrierten Halbleiterschaltung aufzusetzende Röhre (90, 91) der Abdeckung der nicht zu beschichtenden Bereiche und der Raum zwischen den Röhren (90,91; 96,97) der Abführung der gasförmigen Atmosphäre dient.
2. Vorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß die äußere Röhre (90, 91) eine Kühlvorrichtung (105, 106) zur Kühlung des abgesaugten Gases enthält.
DE2620707A 1975-05-12 1976-05-11 Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung Expired DE2620707C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/576,517 US4041896A (en) 1975-05-12 1975-05-12 Microelectronic circuit coating system

Publications (3)

Publication Number Publication Date
DE2620707A1 DE2620707A1 (de) 1976-11-18
DE2620707B2 true DE2620707B2 (de) 1978-09-21
DE2620707C3 DE2620707C3 (de) 1979-05-23

Family

ID=24304755

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2620707A Expired DE2620707C3 (de) 1975-05-12 1976-05-11 Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung

Country Status (8)

Country Link
US (1) US4041896A (de)
JP (1) JPS51135471A (de)
CA (1) CA1059648A (de)
DE (1) DE2620707C3 (de)
FR (1) FR2311404A1 (de)
GB (1) GB1519251A (de)
IT (1) IT1060415B (de)
NL (1) NL7604980A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4401053A (en) * 1981-07-17 1983-08-30 Riley Thomas J Coating fixture

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2704992A (en) * 1951-12-28 1955-03-29 Erie Resistor Corp Gas plating apparatus
US2879188A (en) * 1956-03-05 1959-03-24 Westinghouse Electric Corp Processes for making transistors
US3117025A (en) * 1961-08-31 1964-01-07 Space Technology Lab Inc Thin filming apparatus
BE623233A (de) * 1961-10-12 1900-01-01
US3207126A (en) * 1961-11-14 1965-09-21 Byron Ernest Mask changer means for vacuum deposition device
US3312572A (en) * 1963-06-07 1967-04-04 Barnes Eng Co Process of preparing thin film semiconductor thermistor bolometers and articles
US3276423A (en) * 1963-10-04 1966-10-04 David P Triller Pattern mask for use in making thin film circuitry
US3465209A (en) * 1966-07-07 1969-09-02 Rca Corp Semiconductor devices and methods of manufacture thereof
FR1518843A (fr) * 1967-02-13 1968-03-29 Radiotechnique Coprim Rtc Dispositif pour le dépôt de couches minces sur des supports semi-conducteurs
US3597834A (en) * 1968-02-14 1971-08-10 Texas Instruments Inc Method in forming electrically continuous circuit through insulating layer
US3621812A (en) * 1969-06-18 1971-11-23 Texas Instruments Inc Epitaxial deposition reactor
US3647533A (en) * 1969-08-08 1972-03-07 Us Navy Substrate bonding bumps for large scale arrays
US3785046A (en) * 1970-03-06 1974-01-15 Hull Corp Thin film coils and method and apparatus for making the same
US3678892A (en) * 1970-05-19 1972-07-25 Western Electric Co Pallet and mask for substrates

Also Published As

Publication number Publication date
US4041896A (en) 1977-08-16
NL7604980A (nl) 1976-11-16
FR2311404A1 (fr) 1976-12-10
GB1519251A (en) 1978-07-26
JPS51135471A (en) 1976-11-24
CA1059648A (en) 1979-07-31
DE2620707A1 (de) 1976-11-18
DE2620707C3 (de) 1979-05-23
IT1060415B (it) 1982-08-20
FR2311404B1 (de) 1979-03-02

Similar Documents

Publication Publication Date Title
DE2153103B2 (de) Verfahren zur Herstellung integrierter Schattungsanordnungen sowie nach dem Verfahren hergestellte integrierte Schaltungsanordnung
EP0010771A1 (de) Kapazitiver Feuchtefühler
DE2101028C2 (de) Verfahren zum Herstellen einer Mehrzahl von Halbleiterbauelementen
DE3034900C2 (de) Verfahren zur Herstellung einer aluminiumhaltigen Leiterschicht
DE2548563A1 (de) Verfahren zum herstellen eines kondensators
DE2052221B2 (de) Verfahren zum erzeugen einer siliciumoxidschicht auf einem siliciumsubstrat und vorrichtung zur durchfuehrung dieses verfahrens
DE3715231A1 (de) Messvorrichtung zur bestimmung der temperatur von halbleiterkoerpern, verfahren zur herstellung der messvorrichtung und verfahren zur bestimmung der temperatur von halbleiterkoerpern waehrend temperprozessen
DE2620707C3 (de) Vorrichtung zur Herstellung eines Überzuges auf einer integrierten Halbleiterschaltung
DE102005028935B4 (de) Bauelement mit variabler Kapazität, welches eine hohe Genauigkeit aufweist
DE2039027C3 (de) Halbleiteranordnung mit einem Träger aus Isoliermaterial, einem Halbleiterbauelement und einem Anschlußfleck
DE2404758A1 (de) Verfahren zum serienmaessigen herstellen elektrischer bauelemente
DE1764937C3 (de) Verfahren zur Herstellung von Isolationsschichten zwischen mehrschichtig übereinander angeordneten metallischen Leitungsverbindungen für eine Halbleiteranordnung
DE2945385A1 (de) Halbleiter-anordnung und verfahren zu ihrer herstellung
DE19902769A1 (de) Keramisches, passives Bauelement
DE1564136C3 (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE1278194B (de) Verfahren zum Vakuumaufdampfen von stabilen duennen Siliciummonoxyd-Schichten
DE1521337C3 (de) Verfahren zur Siliciumnitrid-Filmschichtbildung
DE1589852A1 (de) Halbleiteranordnung und Verfahren zu seiner Herstellung
DE2227342A1 (de) Verfahren zum herstellen eines musters hoher aufloesung
DE10051933A1 (de) Reaktionskammer zum Formen eines Halbleiter-Wafers
DE2529484B2 (de) Verfahren und Vorrichtung zum epitaktischen Abscheiden von Silicium auf einem Substrat
DE2837200C2 (de) Verfahren zum Umhüllen von elektrischen Schichtkondensatoren
DE2017930A1 (de) Elektrischer Kondensator
DE1764282C3 (de) Halbleiteranordnung mit einer eine Aluminiumschicht tragenden, aus Siliziumoxid bestehenden Schicht
DE1954135A1 (de) Verfahren zum Herstellen einer Halbleiteranordnung

Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee