DE2619159C2 - Fehlererkennungs- und Korrektureinrichtung - Google Patents

Fehlererkennungs- und Korrektureinrichtung

Info

Publication number
DE2619159C2
DE2619159C2 DE2619159A DE2619159A DE2619159C2 DE 2619159 C2 DE2619159 C2 DE 2619159C2 DE 2619159 A DE2619159 A DE 2619159A DE 2619159 A DE2619159 A DE 2619159A DE 2619159 C2 DE2619159 C2 DE 2619159C2
Authority
DE
Germany
Prior art keywords
bits
error
bit
parity
correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2619159A
Other languages
German (de)
English (en)
Other versions
DE2619159A1 (de
Inventor
Joseph Thomas Boxborough Mass. West
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of DE2619159A1 publication Critical patent/DE2619159A1/de
Application granted granted Critical
Publication of DE2619159C2 publication Critical patent/DE2619159C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE2619159A 1975-05-07 1976-04-30 Fehlererkennungs- und Korrektureinrichtung Expired DE2619159C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/575,357 US4005405A (en) 1975-05-07 1975-05-07 Error detection and correction in data processing systems

Publications (2)

Publication Number Publication Date
DE2619159A1 DE2619159A1 (de) 1976-11-18
DE2619159C2 true DE2619159C2 (de) 1982-05-27

Family

ID=24299995

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2619159A Expired DE2619159C2 (de) 1975-05-07 1976-04-30 Fehlererkennungs- und Korrektureinrichtung

Country Status (6)

Country Link
US (1) US4005405A (OSRAM)
JP (1) JPS51146144A (OSRAM)
CA (1) CA1056952A (OSRAM)
DE (1) DE2619159C2 (OSRAM)
FR (1) FR2310593A1 (OSRAM)
GB (1) GB1511806A (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3807596A1 (de) * 1988-03-08 1989-09-21 Siemens Ag Verfahren und anordnung zur fehlererkennung bei binaeren datenwoertern

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US4077565A (en) * 1976-09-29 1978-03-07 Honeywell Information Systems Inc. Error detection and correction locator circuits
US4072853A (en) * 1976-09-29 1978-02-07 Honeywell Information Systems Inc. Apparatus and method for storing parity encoded data from a plurality of input/output sources
US4100403A (en) * 1977-04-25 1978-07-11 International Business Machines Corporation Method and means for discriminating between systematic and noise-induced error in data extracted from word organized memory arrays
US4139148A (en) * 1977-08-25 1979-02-13 Sperry Rand Corporation Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory
US4171765A (en) * 1977-08-29 1979-10-23 Data General Corporation Error detection system
DE2811318C2 (de) * 1978-03-16 1983-02-17 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Übertragung und Speicherung eines Teilwortes
US4166211A (en) * 1978-04-03 1979-08-28 Burroughs Corporation Error control system for named data
GB2023895B (en) * 1978-06-21 1982-10-13 Data General Corp Error detection circuit
GB2035014B (en) * 1978-11-06 1982-09-29 British Broadcasting Corp Cyclic redundancy data check encoding method and apparatus
US4253182A (en) * 1979-04-09 1981-02-24 Sperry Rand Corporation Optimization of error detection and correction circuit
WO1981001209A1 (fr) * 1979-10-29 1981-04-30 Vinnitsky Politekhn I Procede et dispositif de detection d'erreurs dans des donnees en masse representees en code p
US4363125A (en) * 1979-12-26 1982-12-07 International Business Machines Corporation Memory readback check method and apparatus
US4380812A (en) * 1980-04-25 1983-04-19 Data General Corporation Refresh and error detection and correction technique for a data processing system
US4335459A (en) * 1980-05-20 1982-06-15 Miller Richard L Single chip random access memory with increased yield and reliability
US4346474A (en) * 1980-07-03 1982-08-24 International Business Machines Corporation Even-odd parity checking for synchronous data transmission
US4417339A (en) * 1981-06-22 1983-11-22 Burroughs Corporation Fault tolerant error correction circuit
JP2572487B2 (ja) * 1989-11-16 1997-01-16 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン データの磁気記録方法
US5392294A (en) * 1991-03-08 1995-02-21 International Business Machines Corporation Diagnostic tool and method for locating the origin of parasitic bit faults in a memory array
US5426655A (en) * 1991-07-16 1995-06-20 International Business Machines Corporation Method and apparatus for magnetic recording of data
US5379411A (en) * 1991-11-15 1995-01-03 Fujitsu Limited Fault indication in a storage device array
US5455942A (en) * 1992-10-01 1995-10-03 International Business Machines Corporation Partial page write detection for a shared cache using a bit pattern written at the beginning and end of each page
US5453999A (en) * 1994-04-26 1995-09-26 Unisys Corporation Address verification system using parity for transmitting and receiving circuits
GB2289779B (en) * 1994-05-24 1999-04-28 Intel Corp Method and apparatus for automatically scrubbing ECC errors in memory via hardware
US5673419A (en) * 1995-05-19 1997-09-30 Simple Technology, Incorporated Parity bit emulator with write parity bit checking
US5987628A (en) * 1997-11-26 1999-11-16 Intel Corporation Method and apparatus for automatically correcting errors detected in a memory subsystem
EP1438662A2 (en) * 2001-10-11 2004-07-21 Altera Corporation Error detection on programmable logic resources
US6976197B2 (en) * 2001-10-25 2005-12-13 International Business Machines Corporation Apparatus and method for error logging on a memory module
US7278079B2 (en) * 2002-04-12 2007-10-02 Broadcom Corporation Test head utilized in a test system to perform automated at-speed testing of multiple gigabit per second high serial pin count devices
US7363557B2 (en) * 2002-04-12 2008-04-22 Broadcom Corporation System for at-speed automated testing of high serial pin count multiple gigabit per second devices
DE60306008T2 (de) * 2002-04-12 2007-01-11 Broadcom Corp., Irvine Einrichtungen und Verfahren für die Hochgeschwindigkeitsprüfung von Schaltungen mit hoher Pinzahl und mehreren Gigabit
US7502326B2 (en) * 2002-04-12 2009-03-10 Broadcom Corporation Methods used to simultaneously perform automated at-speed testing of multiple gigabit per second high serial pin count devices
US7328377B1 (en) 2004-01-27 2008-02-05 Altera Corporation Error correction for programmable logic integrated circuits
US7389465B2 (en) * 2004-01-30 2008-06-17 Micron Technology, Inc. Error detection and correction scheme for a memory device
US20070050668A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Test mode to force generation of all possible correction codes in an ECC memory
US7506226B2 (en) * 2006-05-23 2009-03-17 Micron Technology, Inc. System and method for more efficiently using error correction codes to facilitate memory device testing
US20070283208A1 (en) * 2006-06-01 2007-12-06 International Business Machines Corporation Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus diagnostic features
US20070283223A1 (en) * 2006-06-01 2007-12-06 International Business Machines Corporation Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with all checkbits transferred last
US20070283207A1 (en) * 2006-06-01 2007-12-06 International Business Machines Corporation Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements
US7721178B2 (en) * 2006-06-01 2010-05-18 International Business Machines Corporation Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code
CN104145249B (zh) 2012-02-29 2017-08-15 飞思卡尔半导体公司 用于调试计算机程序的方法和系统
US9275757B2 (en) * 2013-02-01 2016-03-01 Scaleo Chip Apparatus and method for non-intrusive random memory failure emulation within an integrated circuit
US9146809B2 (en) 2013-10-07 2015-09-29 Macronix International Co., Ltd. ECC method for double pattern flash memory
US9535785B2 (en) 2014-01-17 2017-01-03 Macronix International Co., Ltd. ECC method for flash memory
US10108487B2 (en) 2016-06-24 2018-10-23 Qualcomm Incorporated Parity for instruction packets
DE102018126051A1 (de) * 2018-01-12 2019-07-18 Taiwan Semiconductor Manufacturing Co. Ltd. Neuartige Speichervorrichtung
CN109753369B (zh) * 2018-12-28 2023-10-24 上海微阱电子科技有限公司 一种寄存器及内存中顺序数组的数据编码及校验方法

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US3218612A (en) * 1961-11-09 1965-11-16 Ibm Data transfer system
US3439331A (en) * 1965-06-16 1969-04-15 Ibm Error detection and correction apparatus
US3474413A (en) * 1965-11-22 1969-10-21 Dryden Hugh L Parallel generation of the check bits of a pn sequence
US3478313A (en) * 1966-01-20 1969-11-11 Rca Corp System for automatic correction of burst-errors
US3585378A (en) * 1969-06-30 1971-06-15 Ibm Error detection scheme for memories
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
US3648239A (en) * 1970-06-30 1972-03-07 Ibm System for translating to and from single error correction-double error detection hamming code and byte parity code
US3697949A (en) * 1970-12-31 1972-10-10 Ibm Error correction system for use with a rotational single-error correction, double-error detection hamming code
US3814921A (en) * 1972-11-15 1974-06-04 Honeywell Inf Systems Apparatus and method for a memory partial-write of error correcting encoded data
US3851306A (en) * 1972-11-24 1974-11-26 Ibm Triple track error correction
US3825893A (en) * 1973-05-29 1974-07-23 Ibm Modular distributed error detection and correction apparatus and method
US3836957A (en) * 1973-06-26 1974-09-17 Ibm Data storage system with deferred error detection
JPS5440187B2 (OSRAM) * 1973-07-25 1979-12-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3807596A1 (de) * 1988-03-08 1989-09-21 Siemens Ag Verfahren und anordnung zur fehlererkennung bei binaeren datenwoertern

Also Published As

Publication number Publication date
FR2310593A1 (fr) 1976-12-03
FR2310593B1 (OSRAM) 1983-02-04
GB1511806A (en) 1978-05-24
CA1056952A (en) 1979-06-19
US4005405A (en) 1977-01-25
JPS51146144A (en) 1976-12-15
JPS5438028B2 (OSRAM) 1979-11-19
DE2619159A1 (de) 1976-11-18

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Legal Events

Date Code Title Description
OGA New person/name/address of the applicant
D2 Grant after examination