DE2551961A1 - Verfahren zur herstellung eines halbleiterbauelementes - Google Patents
Verfahren zur herstellung eines halbleiterbauelementesInfo
- Publication number
- DE2551961A1 DE2551961A1 DE19752551961 DE2551961A DE2551961A1 DE 2551961 A1 DE2551961 A1 DE 2551961A1 DE 19752551961 DE19752551961 DE 19752551961 DE 2551961 A DE2551961 A DE 2551961A DE 2551961 A1 DE2551961 A1 DE 2551961A1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor component
- semiconductor
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/025—Deposition multi-step
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13365874A JPS5329555B2 (de) | 1974-11-22 | 1974-11-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE2551961A1 true DE2551961A1 (de) | 1976-05-26 |
Family
ID=15109906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19752551961 Pending DE2551961A1 (de) | 1974-11-22 | 1975-11-19 | Verfahren zur herstellung eines halbleiterbauelementes |
Country Status (3)
Country | Link |
---|---|
US (1) | US4045249A (de) |
JP (1) | JPS5329555B2 (de) |
DE (1) | DE2551961A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5485029A (en) * | 1994-06-30 | 1996-01-16 | International Business Machines Corporation | On-chip ground plane for semiconductor devices to reduce parasitic signal propagation |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240977A (en) * | 1975-09-26 | 1977-03-30 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
US4179311A (en) * | 1977-01-17 | 1979-12-18 | Mostek Corporation | Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides |
US4099987A (en) * | 1977-07-25 | 1978-07-11 | International Business Machines Corporation | Fabricating integrated circuits incorporating high-performance bipolar transistors |
US4195307A (en) * | 1977-07-25 | 1980-03-25 | International Business Machines Corporation | Fabricating integrated circuits incorporating high-performance bipolar transistors |
NL7709363A (nl) * | 1977-08-25 | 1979-02-27 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd onder toepassing van een dergelijke werkwijze. |
FR2454698A1 (fr) * | 1979-04-20 | 1980-11-14 | Radiotechnique Compelec | Procede de realisation de circuits integres a l'aide d'un masque multicouche et dispositifs obtenus par ce procede |
JPS5946065A (ja) * | 1982-09-09 | 1984-03-15 | Toshiba Corp | 半導体装置の製造方法 |
US5236856A (en) * | 1991-08-30 | 1993-08-17 | Micron Technology, Inc. | Method for minimizing diffusion of conductivity enhancing impurities from one region of polysilicon layer to another region and a semiconductor device produced according to the method |
US5273924A (en) * | 1991-08-30 | 1993-12-28 | Micron Technology, Inc. | Method for forming an SRAM by minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another region |
US6780718B2 (en) * | 1993-11-30 | 2004-08-24 | Stmicroelectronics, Inc. | Transistor structure and method for making same |
US5998277A (en) * | 1998-03-13 | 1999-12-07 | Texas Instruments - Acer Incorporated | Method to form global planarized shallow trench isolation |
US6175147B1 (en) * | 1998-05-14 | 2001-01-16 | Micron Technology Inc. | Device isolation for semiconductor devices |
TW495859B (en) * | 2001-07-23 | 2002-07-21 | Mosel Vitelic Inc | Method for preventing gate oxide thinning |
JP4556376B2 (ja) * | 2001-09-12 | 2010-10-06 | セイコーエプソン株式会社 | 半導体基板の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622382A (en) * | 1969-05-05 | 1971-11-23 | Ibm | Semiconductor isolation structure and method of producing |
US3666548A (en) * | 1970-01-06 | 1972-05-30 | Ibm | Monocrystalline semiconductor body having dielectrically isolated regions and method of forming |
US3947299A (en) * | 1971-05-22 | 1976-03-30 | U.S. Philips Corporation | Method of manufacturing semiconductor devices |
US3748187A (en) * | 1971-08-03 | 1973-07-24 | Hughes Aircraft Co | Self-registered doped layer for preventing field inversion in mis circuits |
-
1974
- 1974-11-22 JP JP13365874A patent/JPS5329555B2/ja not_active Expired
-
1975
- 1975-11-19 DE DE19752551961 patent/DE2551961A1/de active Pending
- 1975-11-24 US US05/634,783 patent/US4045249A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5485029A (en) * | 1994-06-30 | 1996-01-16 | International Business Machines Corporation | On-chip ground plane for semiconductor devices to reduce parasitic signal propagation |
Also Published As
Publication number | Publication date |
---|---|
JPS5329555B2 (de) | 1978-08-22 |
JPS5160474A (de) | 1976-05-26 |
US4045249A (en) | 1977-08-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OHN | Withdrawal |