DE2525529A1 - SEMICONDUCTOR ARRANGEMENT WITH COMPLEMENTARY TRANSISTOR STRUCTURES AND PROCESS FOR THEIR PRODUCTION - Google Patents

Description

PIIN. 7598

■ - 1 - 16-5-1975 voor / jv / jb

vorai £

"Semiconductor arrangement with complementary transistor structures and procedures for their preparation ".

The invention relates to a

Semiconductor arrangement with a Köx'per with at least a first epitaxial semiconductor layer of a most severe conductivity type and one thereon lying second epitaxial semiconductor layer from second opposite conductivity type, which is adjacent to a surface of the body, which arrangement contains at least two complementary bipolar transistor structures that are electrically isolated from one another, wherein the base region of the first transistor structure through at least a portion of the first epitaxial

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Layer and the base region of the second transistor structure through at least part of the second epitaxial layer is formed.

The invention further relates to a method for producing such a semiconductor arrangement.

As usual, complementary transxstor structures are to be understood as two transxstor structures, opposite to their corresponding zones Have conductivity types (npn and pnp).

Semiconductor arrangements of the type described are for example from the French patent specification 1,448,766 known.

Attempts have been made in many ways, using two or more epitaxial Layers integrated circuits with complementary To produce transxstor structures. These Transxstor structures can either be independent be used as a transistor or part of a complicated semiconductor circuit element such as e.g. a pnpn thyristor.

However, so far it has proven to be very

proved difficult to arrange complementary transistor structures in such a circuit, such

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that both transistor structures have a large gain factor and also in other respects, namely with regard to the frequency range, have comparable and favorable electrical properties. So In many cases it has proven impossible to use both complementary transistor structures with one epitaxial base (which makes it particularly suitable for operation at a relatively low frequency are to be carried out. In other cases, as described in the aforementioned French patent, in which two complementary transistor structures with an epitaxial base are obtained, Mesa structures must necessarily be used. This is disadvantageous because it is generally preferred, particularly with regard to the metallization integrated circuits with a flat or practically flat surface can be used.

The invention aims, inter alia, to provide a semiconductor device with a new structure, eliminating the above-described in known arrangements occurring disadvantages can be avoided or at least reduced to a considerable extent. The invention The aim is also to create a semiconductor device that can be implemented in a simple manner

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an integrated circuit with at least two complementary Low frequency transistors enables and is particularly well suited for use in integrated circuits with dielectric isolation.

The invention is based inter alia on the

Realization that through appropriate use of the named epitaxial layers for the formation of both the base as well as the emitter zone of the same transistor can have a transistor structure, which is not only particularly good for assembling with a complementary transistor structure with epitaxial Basis is suitable, but also has electrical properties that are at least as favorable as are known transistor structures.

A semiconductor device of the initially

described type is characterized according to the invention in that both transistor structures in Islands are arranged that adjoin the same flat surface of the body and through a barrier layer separated from the rest of the body; that the collector zone of the second transistor structure is formed by at least part of the first epitaxial layer, and that the first transistor structure on the surface

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contains zendes semiconductor region of the second conductivity type, which adjoins the surface, through Parts of the first and the second epitaxial layer formed area within the body practically completely surrounds and forms the collector zone, at least one extending from the surface to the first epitaxial layer extending from said semiconductor region from the second conductivity ^ type separate connection inches of the first conductivity type is present, which is higher than the first epitaxial layer is doped and part of the second epitaxial layer, which is the emitter zone forms, completely encloses.

The semiconductor arrangement according to the invention has two complementary transistor structures, both designed with an epitaxial base and thus suitable for low-frequency operation.

The said first transistor structure, · whose emitter zone passes through part of the second epitaxial Layer is formed has, inter alia, the advantage that the injection of minority charge carriers from the emitter zone is almost completely in one direction across the surface and practical does not take place in the lateral direction at all. This is

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due to the fact that the connection zone of the first conductivity type, which surrounds the emitter zone, "at least near the surface higher and generally considerably higher than that" between the Emitter zone and the collector zone lying active part of the base zone is doped. Another advantage of said first transistor structure according to the invention consists in that the base zone, excepted at the point of the connecting zone, not at any one Place to the surface. As a result, the influence of surface recombination is minimal. Through the mentioned circumstances can affect the electrical properties the first transistor structure at least as cheap as the more common, possibly an epitaxial base zone containing transistor structures.

By applying the invention,

LJ

Furthermore, an albleiteranordiiuiig with complementary Get transistor structures with a flat or practically flat surface, because both the first as also the second epitaxial layer is part of both Form transistor structures so that mesa structures can be avoided.

Although, as will become apparent from an example to be described below, the

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called connection zone of the first conductivity type also in other ways, e.g. '. through an insulating layer, may be separated from the region of the second conductivity type, the connection zone is preferably from this area separated by part of the second epitaxial layer.

Said barrier layer can e.g.

be formed by a pn junction, which in the operating state is biased in the »reverse direction. According to an important preferred embodiment however, the barrier layer is formed by an insulating layer of dielectric material. the complementary transistor structures are thereby electrically isolated under all circumstances, whereby it it is not necessary to use voltages to be applied to maintain this insulation during operation.

To reduce the collector resistance of the first transistor structure while maintaining it a relatively high base-collector breakdown voltage, the area mentioned is from second conductivity type preferably at least in its part adjoining the second epitaxial layer higher than the adjoining part of the

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second epitaxial layer doped. It is also advantageous to improve the emitter effect said emitter zone at least partially and preferably completely higher than the surrounding part doped the second epitaxial layer.

In all of the above cases

the semiconductor arrangement is preferably also designed in such a way that the second, complementary to the first Transistor structure a region of the first conductivity type adjoining the surface contains, which is adjacent to the surface, by parts of the first and the second epitaxial Layer formed area within the body practically.completely surrounds. This allows the collector zone the second complementary transistor structure contacted in a simple manner on the surface and the collector series resistance is reduced.

A semiconductor device according to the invention, in which the body consists entirely of single-crystal semiconductor material is further preferably characterized in that said area of the first conductivity type and the called area of the second conductivity type both

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contain a buried layer that covers a zone of the same conductivity type with the surface is connected and with the unigigenden part of the semiconductor body forms a pn junction ending at the surface. This makes the complementary Transistor structures each isolated from the rest of the body.

A

Structure with three epitaxial layers used, wherein the first epitaxial layer lies on a third epitaxial layer which is on a Substrate is deposited and with this a pn junction forms. Although such a preferred embodiment also applies to dielectrically isolated ones complementary transistor structures are used can, it is often particularly advantageous in the implementation of 'fransist' isolated by pn junctions ο r structures, the presence of the third epitaxial layer contributing to the tolerances the formation of the necessary buried layers in particular.

The invention also relates

to a particularly advantageous method of production a semiconductor device according to the invention

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with dielectrically isolated transistor structures. This method is characterized in that a first epitaxial layer from an ice Conductivity type and a second epitaxial layer lying thereon of the second conductivity type are deposited on a carrier body, with at least two of the epitaxial layers Islands are formed over which an insulating dielectric layer is applied; that in one Island a transistor structure and a transistor structure complementary to this in the other island is formed, and that before the production of the dielectric layer by the introduction of doping- Substances one island with a surface layer of the first conductivity type and the other island with a surface layer of the second conductivity type is provided.

Some embodiments of the invention are shown in the drawing and are described in more detail below. Show it:

Fig. 1 schematically in cross section a semiconductor arrangement according to the invention,

Figures 2-5 schematically in cross section on successive stages of the Ilex-s division of the Aiiord-

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after. Fig. 1 using the inventive Procedure,

6 shows, schematically in cross section, a modification of the arrangement according to FIG. 1,

Fig. 7 is a schematic, in cross section a further modification of the arrangement according to FIG. "1,

Fig. 8 schematically in Quei-section and

partly diagrammatically another embodiment a semiconductor arrangement according to the invention,

Figures 9-1 '+ schematically in cross section the arrangement of FIG. 8 in successive Stages of their manufacture,

Figures 15 »16 and 17 schematically in

Cross-section and partly diagrammatically further embodiments a semiconductor device according to the invention, and

18 shows a further embodiment of a semiconductor arrangement in cross section according to the invention.

The figures are schematic and not

Drawn to scale, with the sake of clarity in particular, the dimensions in the thickness direction are shown exaggerated. With the in cross section Halhieiter areas shown are areas from

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same conductivity type in the same direction hatched. Furthermore, the boundaries of the various zones, in particular those caused by doping, E.g. zones formed by diffusion, shown not to scale, but purely schematically. In the figures, there is in particular the one occurring parallel to the surface due to lateral diffusion Expansion of the various zones completely neglected for the sake of clarity.

Except for the boundaries between epitaxial layers and between an epitaxial layer Layer and the substrate, which are always shown with full lines, are boundaries between areas of the same conductivity type, but with different doping, generally with a dashed line and pn junctions with represented by a full line.

Fig. 1 shows schematically in cross section a semiconductor device according to the invention. the Arrangement contains a body made of a carrier body 1 made of polycrystalline silicon, a first epitaxial Silicon layer 2, which in this example is p-type, and a second layer lying thereon η-conductive epitaxial silicon layer 3 · Though

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In this example, if the above-mentioned conductivity types are selected for layers 2 and 3, these conductivity types may also be chosen the other way round, provided that they are opposite to one another. The second η-conductive epitaxial layer 3 adjoins a surface h of the body.

The arrangement contains two mutually electrically insulated complementary bipolar transistor structures, namely a first npn transistor structure T ₁ , the base zone of which is formed by the first epitaxial layer 2, and a second (pnp) transistor structure Ύ which is _{complementary to the transistor structure T 1.} whose base zone is formed by the second epitaxial layer 3. According to the invention, the two complementary transistor structures T ₁ and T ₀ are arranged in islands which border the same flat surface (h) of the body and are separated from the rest of the body by a barrier layer, in this example an electrically insulating silicon oxide layer are separated, the collector zone dor the second transistor structure T "dux'ch the first epitaxial .Layer 2 is formed. e en-s. ■

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stjttk ^ - dmrehr 'St.e epitaxial layer 2 ~ is formed. T £ »i result — t —— will. Further to the invention the first transistor structure T containing ₁ a to the surface h bordering layer ·-shaped highly doped ii-type region 6, which is a to the surface bordering h by portions of the epitaxial layers 2 and virtually completely surrounds 3 formed region within the body and forms the collector zone of the first transistor structure. In this case, there is a p-conductive connection zone 7 which extends from the surface h to the first epitaxial layer 2 and is separated from the region 6 by a part of the second epitaxial layer 3, which is more heavily doped than the first epitaxial layer 2 and a part 8 of the second epitaxial layer 3, which forms the emitter zone, completely surrounds.

The collector zone of the second complementary transistor structure T "is contacted by means of a highly doped p-conductive layer 9 which, within the island in which T_ is arranged, practically completely surrounds the epitaxial layers 2 and 3 and extends up to the surface h ,

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at which it can be contacted by means of a metal layer 10. The emitter of the transistor structure T 1 is a p-conducting zone 11 produced in layer 3, for example by diffusion or by ion implantation, which is electrically contacted by a metal layer 12. If necessary, contact is made with the base zone of the transistor structure T "via contact diffusion by means of a metal layer 13, while the collector zone and the emitter zone 8 of the transistor structure T by means of metal layers ΛΗ and 15 and the base zone 2 of this structure via the connection zone 7 by means of a metal layer 16.

The semiconductor device described

has a practically flat surface and contains two complementary transistors T ₁ and T ″, both of which have an epitaxial base and as such are suitable for operation at a relatively low frequency. In the example described, both transistor structures are designed as simple transistors. It is clear, however, that one or both transistors can also be designed, for example, as thyristors, for example by forming an additional p-conductive zone in the nleä tendon zone 8, which is completely surrounded by zone 8.

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and that contacts on this p-conductive zone and on zone 6 as well as a control electrode on one of zones 7 or 8 are produced. The thyristor obtained in this way then contains a transistor structure T ₁ which is complementary to the transistor structure T ".

The arrangement described can advantageously be produced according to the invention as follows. It is assumed (see FIG. 2) from a highly doped single-crystal η-conductive silicon substrate 17 with a specific resistance of, for example, 0.001 cm and a thickness of, for example, 250 μm. A first p-conductive silicon layer 2 with a thickness of about 15 μm and a specific resistance of, for example, k cm and a second η-conductive silicon layer 3 having a thickness of about TO / µm and a specific resistance of, for example, 1.5 .cm is epitaxially grown. Then on the layer 3 (if desired after the formation of a thin oxide layer with a thickness of about 0.1 / .mu.m, which is not shown here) a silicon

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nitride layer 18 * ^r a 0.15 / um in the usual way deposited with a thickness of eti, after which a is about 150 / deposited by thick layer 19 of polycrystalline] silicon on the nitride layer 18 from the gas phase. The structure according to FIG. 2 is thus obtained. The layers 18 and 19 together form an auxiliary carrier layer.

The highly doped substrate 17 is then, for example, by applying a selective chemical or electrochemical etching treatment with a specifically high etching speed for highly doped n-conductive Silicon removed, after which from the epltaktischeii Layers 2 and 3 conical by masking and etching Areas I and II (see Fig. 3) are formed. The Siliciunmitridschicht 18 protects during this etching process sees the polycrystalline silicon 19th

The island II is then e.g.

pyrolytic ^ deposition of a silicon oxide layer (Silox) and the etching away of part of this layer provided with a mask 20 so that the island I is uncoated. The island I is then covered with a highly doped η-conductive surface layer 6 e.g. provided by the diffusion of arsenic. So is

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the state shown in Fig. 3 is obtained.

The island I is then masked in the same way and becomes the island through a boron diffusion II provided with a p-conductive surface layer 9, after which on the whole a layer 5 of pyrolytic silicon oxide with a thickness of 1 to 2 / to be knocked down. This oxide layer 5 can, if desired, also 'by thermal oxidation and are then naturally absent between islands I and II.

A layer of polycrystalline silicon with a thickness of approximately 250 μm is then deposited again from the gas phase on the oxide layer 5, which layer forms the final carrier layer 1 (see FIG. H) .

The polycrystalline silicon layer 19 is now removed, for example, by etching with an HP-IINO "solution, after which the silicon nitride layer 18 is removed by etching with phosphoric acid at about 180 ° C. as described. A silicon oxide layer is then deposited again on the surface k exposed in this way, in which initially the connecting man 7 is etched in a photographic way, for example by means of a boron diffusion, in order to diffuse it.

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A diffusion window is then etched into the oxide layer to diffuse in the less deep p-conductive emitter zone 11 of the complementary second transistor structure and to diffuse in a p-conductive zone 21 (see FIG. 5). Zones 11 and 21 can be diffused in at the same time, with the zone 21 serves to facilitate contacting the collector contact layer 9 without inspects the risk that the ~ jm Üborgang between deν layer 9 and the layer is short-circuited at the surface · 3 (see also Fig.- 1).

Through a selective diffusion of a

Donor, such as phosphorus, into the zone 8, the doping of the emitter region to improve the EmitterwirkuJig d rl] ÖHT may be.

After etching contact windows in

another deposited layer 22 of silicon oxide or from another insulating material and after metalization, e.g. by vapor deposition of aluminum, the structure according to FIG. 1 is obtained.

It is evident that the arrangement, apart from the two islands I and II shown, still exists can contain more islands in which further active and / or passive semiconductor circuit elements are

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are uoramon.

Although in the example just described the active part of the base of the transistor T _{1 is formed} by the epitaxial layer 2 in the form in which it is deposited, this transistor can, if desired, be made suitable for a higher frequency range by a small change in manufacture For this purpose, for example, zones 7 and 8 are arranged in such a way that initially a p-conductive zone 7 is generated by, for example, an on-board diffusion in the entire area occupied by zones 7 and 8 and over part of the thickness of layer 2 , after which the emitter zone 8 is obtained by a phosphorus diffusion of higher doping, which compensates for the boron diffusion. The section corresponding to FIG. 1 then looks like the "" in FIG. 6, in which the arrangement has a thinner effective base zone and is therefore suitable for higher frequencies.

Instead of in the form of the structures described, the arrangement according to the invention can under Use of dielectric insulation can find application in various other forms. An example is shown schematically in cross section in FIG.

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posed. In this example, the transistor structures T ₁ and T ″ are also arranged in semiconductor islands I and II, which are separated from the remaining part of the Köx-pers 80, for example made of polycrystalline silicon, by an insulating dielectric layer 5 made of silicon oxide. The islands I and II in this example consist partly of highly doped polycrystalline silicon (81, 82), while the rest of the islands consist of parts of a first p-conductor epitaxial layer. 2 and a second epitaxial layer 3 is built up, which epitaxial parts are separated in the lateral direction from the surrounding polycrystalline silicon by a wall made of silicon oxide. In this example, the connection zone extends as far as the oxide layer 83 and this layer 83 is separated from the n-conductive donor region (81, 84). Where is 8 ^! An n-lextende zone which is obtained by diffusion from the polycrystalline silicon in dei ¹ epitaxial layer 2 and p-n junction in said layer 2, thus in the monocrystalline region, a · forms. 4 The manner in which dielectric insulation as shown in FIG. 7 can be obtained is described in "Semiconductor Silicon 1973" (Proceedings of the Second International

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Symposium on Silicon Material Science and Technology, May 13-18, 1973, Chicago), pp. 893-904, "A New
Technology for Dielectric Isolation "by Y. Sumitomo et al.

It should also be noted that desirable-

if, for example, in order to achieve a lower collector resistance in all these dielectrically isolated structures between the dielectric layer and the island, a metal layer, for example a Mo ^ bdänschicht, can be formed, which if desired can expand up to
extends to the surface.

Ot) already the dielectric insulation,

which was used in the previous example, has great advantages, it is also very possible to .the semiconductor arrangement according to the invention with the help of the usual isolation by means of blocked pn transients
to execute. An example of such an arrangement is shown partially in section and partially .schecklich in FIG. The corresponding zones in
Figs. 1 to 7 and Fig. 8 are the same
. Reference numerals denoted. The arrangement according to FIG. 8
'contains three transistor structures, one of which
npn structure (Τ) formed by the p-type epitaxial layer 2, the 11-loitoiide epitaxial layer 3 and

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the n-conducting region 6 is formed, forms part of a thyristor which is formed by the regions determining the transistor structure T 1 and by a p-conducting zone 30 produced in the emitter zone 8 of this transistor structure. The transistor T ₁ is likewise of the npn type, while the pnp transistor T _{1 has a} rule that is complementary to the two transistor structures T 1 and T _0. The most important difference with the example according to FIGS. 1 to 7 is that the various transistor structures are electrically separated from one another not by dielectric layers but by pn junctions (31, 32, 33) which are switched in the reverse direction in the operating state . The semiconductor device of FIG. 8 further includes a third p-type epitaxial layer 'jh, the n-conductive on a substrate has increased 35 and form with this a \ m ~ Transition! and on which the epitaxial layers 2 and 3 are tigered. For the sake of clarity, FIG. 8 does not show the metallization on the upper surface, the same as the insulating layer on the upper surface in which the contact windows are formed. As far as the contacting of the Transiεtorstruktüren T. and T _{0 is} concerned, this is

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shown in Fig. lh ; of the thyristor (6,2,8,30), to which the internal transistor structure T_ belongs, the zone 8 is contacted on the surface via a more highly doped contact zone 38 to form an ohin control electrode.

. The production of the semiconductor device of Figure 8 can, for example, by a method carried out, the successive stages Jm cross-section in Figures 9 - are shown lh. It is assumed (see FIG. 9) from an n-conductive donut silicon substrate 35 with a thickness of about 250 μm and a specific resistance of about 5 cm. Using conventional masking and etching processes, a highly doped p-conductor layer ^C JA is obtained locally, for example by diffusion of boron. Then, using known techniques, preferably from the gas phase, an approximately 15 μm thick p-type silicon layer 3 ^ with a specific resistance of approximately 10 cm is epitaxially grown. During this epitaxial growth, the layer 9A diffuses partly into the substrate 35 and partly into the layer 3h .

The layer 3h is then subjected to local arsenic diffusion to form an n-type

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Layer 6Α and a phosphorus diffusion to form an n-conductive insulating zone "} G, which surrounds the layer 9A , subjected (see FIG. 10).

Then a p-

conductive silicon layer 2 grown epitaxially, which has a specific resistance of about 5 .cm. During this pre-growth, the zone 36 diffuses into the layers Jh and 2 and the layer 9A also diffuses further into the layer 'Jh and into the substrate 35. Layer 6A diffuses somewhat into layers 2 and Jh , but because the diffusion rate of arsenic is considerably lower than that of boron and phosphorus, the extent of layer 6A is only small (see FIG. 11).

Then on layer 2

an n-type silicon layer 3 with a thickness of about 10 / µm and a resistivity of about 30 cm epitaxially grown (see Fig. 12). Stretch also in this tactical process of growth the already diffused zones are more or less the end. Boron is then locally introduced into the surface of the layer 3 using the usual masking and diffusion techniques to form the p-conducting Zones 7 and 91 * and the isolation zone 37 diffused,

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after which, for example, the zone is formed by phosphorus diffusion (see Fig. 13) The emitter zone 11 is formed by a relatively slight boron diffusion, after which, for example, by a slight phosphorus diffusion, the zone 8 is doped higher than the surrounding part of the layer 3 (see Fig. 1h). The same phosphorus diffusion can be used to form the texturing contact zone 38 of the thyristor structure containing the transistor structure T (see FIG. 8).

Although for the sake of clarity

this thyristor in Figures 9 - lh omitted, it stands to reason that the zones designated therein by the same reference numerals may be formed ₁ and T ₀ at the same time with the corresponding zones of the structures T, while the zone 30 formed simultaneously with the zone 11 can be. Finally, the surface having a · insulating layer 39, preferably formed of silicon oxide, are etched into the contact window, after which the metallization in the form of, for example Aluminiunischicbteti '(O ειη-ordered is lh as indicated in Fig. Scheniatisch.

Another method of forming a

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The arrangement according to the invention with complementary transistor structures T ₁ and T "or τ and Tp is shown in FIG. 15, in which the parts corresponding to those in FIG. 8 are denoted by the same reference numerals". Here, a third p-conductive epitaxial layer 50 is produced between the n-conductive substrate 35 and the first, here η-conductive, epitaxial layer 2. The 'fran sis tor structure T hx3dot also here a part of a pnpn-'fliyristor, Dj e figure needs no further explanation and the arrangement can be produced in the same way as that according to FIG.

In the pre-gelionden. Examples

An η-conductive substrate was used in FIGS. 8 and 15. Let us assume that in these examples he would know if the 1 , <?. it capable 1 gk ο its tyρ c · η s έΐια 11 i ch er semiconductor regions can be reversed. Such a structure Hesse, however, difficult to realize in silicon in connection with the characteristics of available donors and acceptors, find a useful ALzeptor and donor vu due to the fact sf <clickety that it proves do not look in practice in silicon as nearly possible at which at the same temperature · the acceptor has a lower diffusion—

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speed than the donor. Still will In practice, a p-conductive substrate is usually preferred, since then the substrate is used to ensure a satisfactory insulation can be placed on earth.

FIGS. 16 and 17 show two examples in which a p-conductive substrate 60 and a third η-conductive epitaxial layer 61, which forms a pn junction with the substrate 6o, are used. It is obvious that when realizing the given structures, the person skilled in the art will take the necessary measures to prevent the various buried layers, in particular the layers doped with boron, from diffusing so far in the direction of thickness during epitaxial growth that undesirable effects, partly Collector and base resistances that are too high, base thicknesses that are too small or short circuits occur. It should also be noted that the isolation zones 36 and 37 in FIGS. 9-13, in particular with regard to their extension in a direction transverse to the surface, are shown purely schematically for the sake of clarity and not to scale in every listening position level. The final thickness of these zones, as shown in Figure 8, is the result of all of them

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Heat treatments carried out during the production and the diffusion brought about by it.

Finally, Fig. 18 still shows

schomatisch "conductive p-in cross-section another example Einei ¹ arrangement according to the invention having two substantially similarly constructed structures, said conductive n-using only two epitaxial layers, for example, a p-type layer 2 and a layer 3 on a substrate 70, and two η-conducting regions 6 and 72, a first iipn ~ transistor structure T ₁ (8,2,6) and a second transistor structure T which is complementary to this and which is formed by layers 2 and 3 and the p-conducting zone 71 are obtained are. The transistor structure T_ forms, together with the η-conductive region 72, part of a pnpn thyrstor structure (71 >>3>2> 72), which is contacted in the manner shown in FIG.

It should be evident that the

Invention does not relate to the exemplary embodiments described limited, but that within the scope of the invention, many variants are possible for the person skilled in the art. In particular, you can without being affected by the inventive concept is deviated from, other semiconductor materials than silicon, e.g. Geruianiuiii, III-V compound, such as

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GaAs, etc., and iso layers other than silicon oxide, e.g., alumina or silicon nitride can be used. The epitaxial layers can instead of thermal decomposition of a semiconductor compound also e.g. by direct vapor deposition of the semiconductor material or by epitaxial growth can be generated from the liquid phase. The doping of certain zones can also be through instead of diffusion Ion implantation take place while the diffusions are also carried out from e.g. a doped oxide layer can be. Instead of the doping substances mentioned can, if desired, also use other donor and acceptor materials Find application. Furthermore, the arrangement does not need to be made from one and the same semiconductor material to consist, but they can also be made of various semiconductor materials that form hetoro transitions with one another. Besides that The carrier layers 1, 19 and 80 of FIGS. 1-7 do not have to be made of pelycrystalline silicon exist; these layers can basically be made of any desired insulating or non-insulating material. The arrangements can be on many various ways using known doping methods getting produced. The professional becomes

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In each case, make an expedient choice from the possibilities that arise. In particular, the isolation zones that separate parts of the epitaxial layers from one another, e.g. zones 36 and 37 of FIGS. 8 and 15, do not need over the total thickness of all existing epitaxial layers, but only over the total thickness of the layers with a dome opposite the zone in question to be Lei i f i äliigke tstyp generated.

509882/0695

Claims (1)

PIN CODE. 7598- yz -22-5-1975 PATENT CLAIMS: 1 Λ semiconductor device with a body with at least one first epitaxial semiconductor layer of a first type of conductor capability and a second epitaxial conductor layer on top of the second opposite conductivity type which adjoins a surface of the body, which arrangement has at least two complementary bipolar transistor structures electrically isolated from one another contains, wherein the base region of the first transistor structure through at least a portion of the first epitaxial layer and the base region of the second transistor structure by at least one Part of the second epitaxial layer is formed, characterized in that both transistor structures are arranged in islands which border on the same practically flat surface of the body and separated from the rest of the body by a barrier; that the collector zone of the second transistor structure is formed by at least a part of the epitaxial layer, and that the first transistor structure contains a semiconductor region of the second conductivity type adjoining the surface, which region adjoins the surface, 50 9 8 82/0695 PIN CODE. 7598-33-22-5-1975 by. Parts of the first and second epitaxial Layer completely surrounds part formed within the body and forms the collector zone, at least one extending from the surface to the first epitaxial layer of said one Semiconductor region of the two-tone conductivity type separated Connection zone of the first conductivity type is present, which is more highly doped than the first epitaxial layer and part of the second epitaxial Layer that forms the emitter zone, completely encloses. 2. Semiconductor arrangement according to claim 1, characterized gekennzeiclmet that the connection zone of the region of the second conductivity type by a Part of the second epitaxial layer is separated. 3. Halb.le L terordnung according to claim 1 or 2, characterized by that said barrier layer is formed by an insulating layer of dielectric material. H. Semiconductor arrangement according to one or several of the preceding claims, characterized in that that said area of the second conductivity kcii ts Lyp at least in his- to the second epitaxial Layer, adjoining part higher than the adjoining 5 09882/0695 PHN. - 3h - 22-5-1973 adjacent part of the second epitaxial layer is doped. 5. Semiconductor arrangement according to an odex " several of the preceding claims, characterized in that that the said emitter zone is at least partially and preferably completely higher than dec " surrounding part of the second epitaxial layer is doped. 6 »Semiconductor arrangement according to one or several of the preceding claims, characterized in that the second is complementary to the first Transistor structure contains a region adjacent to the surface of the first conductivity type, which is a adjacent to the surface, formed by parts of the first and the second epitaxial layer Area within the body ex is practically completely surrounding. 7 semiconductor device according to claim 6, in which the body is made entirely of single-crystal semiconductor material consists, characterized in that said area is of the first conductivity type and the said area from the second Lo i tf ähi gko i. t s type both contain a buried layer that covers a zone of the same conductivity type is associated with -! er * OborfJaeche and with the surrounding TcM of the semi- 509882/0695 j-FN. 7 59 δ leitei ^ köi-pers one at the. Surface ending pn junction forms. 8. Semiconductor arrangement according to claim 7> characterized in that the first is epitaxial Layer on a third epitaxial layer which is deposited on a substrate and forms a pn junction with it. 9. A method for manufacturing a semiconductor device after. Claims 3 »characterized by that a first epitaxial layer of the first ■ conductivity type and a second lying thereon epitaxial layer of the second conductivity type are deposited on a carrier body, with at least two islands from the epitaxial layers which are coated with an insulating dielectric light; that in one Island a transistor structure and in the other Island one to this complementary transistor structure is formed and that before the creation of the dielectric Layer by introducing dopants an insol with a surface layer from the first Leitf uhi give its type and the other island with a "surface layer of the second conductivity type will . 509882/0695 Blank page