DE2404146A1 - Digitales, hierarchisch in wenigstens drei hierarchie-stufen aufgebautes speichersystem - Google Patents

Digitales, hierarchisch in wenigstens drei hierarchie-stufen aufgebautes speichersystem

Info

Publication number
DE2404146A1
DE2404146A1 DE2404146A DE2404146A DE2404146A1 DE 2404146 A1 DE2404146 A1 DE 2404146A1 DE 2404146 A DE2404146 A DE 2404146A DE 2404146 A DE2404146 A DE 2404146A DE 2404146 A1 DE2404146 A1 DE 2404146A1
Authority
DE
Germany
Prior art keywords
memory
block
unit
address
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2404146A
Other languages
German (de)
English (en)
Inventor
Brian Jeremy Parsons
Lynne Margret Purcell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hawker Siddeley Dynamics Ltd
Original Assignee
Hawker Siddeley Dynamics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hawker Siddeley Dynamics Ltd filed Critical Hawker Siddeley Dynamics Ltd
Publication of DE2404146A1 publication Critical patent/DE2404146A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)
  • Hardware Redundancy (AREA)
DE2404146A 1973-01-28 1974-01-26 Digitales, hierarchisch in wenigstens drei hierarchie-stufen aufgebautes speichersystem Pending DE2404146A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB4476272A GB1461245A (en) 1973-01-28 1973-01-28 Reliability of random access memory systems
US05/456,647 US3983537A (en) 1973-01-28 1974-04-01 Reliability of random access memory systems

Publications (1)

Publication Number Publication Date
DE2404146A1 true DE2404146A1 (de) 1974-08-01

Family

ID=26265450

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2404146A Pending DE2404146A1 (de) 1973-01-28 1974-01-26 Digitales, hierarchisch in wenigstens drei hierarchie-stufen aufgebautes speichersystem

Country Status (5)

Country Link
US (1) US3983537A (enExample)
DE (1) DE2404146A1 (enExample)
FR (1) FR2215671B3 (enExample)
GB (1) GB1461245A (enExample)
NL (1) NL7401042A (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4150428A (en) * 1974-11-18 1979-04-17 Northern Electric Company Limited Method for providing a substitute memory in a data processing system
US4084230A (en) * 1976-11-29 1978-04-11 International Business Machines Corporation Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
DE2841222A1 (de) * 1978-09-22 1980-03-27 Telefonbau & Normalzeit Gmbh Schaltungsanordnung zur adressierung von modular aufgebauten und erweiterungsfaehigen daten-speicheranordnungen
US4254463A (en) * 1978-12-14 1981-03-03 Rockwell International Corporation Data processing system with address translation
US4293910A (en) * 1979-07-02 1981-10-06 International Business Machines Corporation Reconfigurable key-in-storage means for protecting interleaved main storage
GB2062912B (en) * 1979-09-29 1983-09-14 Plessey Co Ltd Data processing system including internal register addressing arrangements
JPS5847793B2 (ja) * 1979-11-12 1983-10-25 富士通株式会社 半導体記憶装置
US4498146A (en) * 1982-07-30 1985-02-05 At&T Bell Laboratories Management of defects in storage media
US4506364A (en) * 1982-09-30 1985-03-19 International Business Machines Corporation Memory address permutation apparatus
US4916603A (en) * 1985-03-18 1990-04-10 Wang Labortatories, Inc. Distributed reference and change table for a virtual memory system
WO1988009995A1 (en) * 1987-06-02 1988-12-15 Hughes Aircraft Company Pipeline memory structure
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US5093807A (en) 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US5155834A (en) * 1988-03-18 1992-10-13 Wang Laboratories, Inc. Reference and change table storage system for virtual memory data processing system having a plurality of processors accessing common memory
KR910008413B1 (ko) * 1989-07-21 1991-10-15 삼성전자 주식회사 메모리 용량 확장장치
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
EP0541288B1 (en) * 1991-11-05 1998-07-08 Fu-Chieh Hsu Circuit module redundacy architecture
US5576554A (en) * 1991-11-05 1996-11-19 Monolithic System Technology, Inc. Wafer-scale integrated circuit interconnect structure architecture
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
EP0654168B1 (en) * 1992-08-10 2001-10-31 Monolithic System Technology, Inc. Fault-tolerant hierarchical bus system
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US6609169B1 (en) 1999-06-14 2003-08-19 Jay Powell Solid-state audio-video playback system
US6567290B2 (en) * 2000-07-05 2003-05-20 Mosaic Systems, Inc. High-speed low-power semiconductor memory architecture
US20050041453A1 (en) * 2003-08-22 2005-02-24 Brazis Paul W. Method and apparatus for reading and writing to solid-state memory
US8130528B2 (en) * 2008-08-25 2012-03-06 Sandisk 3D Llc Memory system with sectional data lines
US8279650B2 (en) 2009-04-20 2012-10-02 Sandisk 3D Llc Memory system with data line switching scheme

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1218406A (en) * 1968-07-04 1971-01-06 Ibm An electronic data processing system
US3633175A (en) * 1969-05-15 1972-01-04 Honeywell Inc Defect-tolerant digital memory system
US3753244A (en) * 1971-08-18 1973-08-14 Ibm Yield enhancement redundancy technique
US3781826A (en) * 1971-11-15 1973-12-25 Ibm Monolithic memory utilizing defective storage cells
US3753242A (en) * 1971-12-16 1973-08-14 Honeywell Inf Systems Memory overlay system
US3755791A (en) * 1972-06-01 1973-08-28 Ibm Memory system with temporary or permanent substitution of cells for defective cells
US3803560A (en) * 1973-01-03 1974-04-09 Honeywell Inf Systems Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system
US3821715A (en) * 1973-01-22 1974-06-28 Intel Corp Memory system for a multi chip digital computer

Also Published As

Publication number Publication date
US3983537A (en) 1976-09-28
NL7401042A (enExample) 1974-07-30
GB1461245A (en) 1977-01-13
FR2215671A1 (enExample) 1974-08-23
FR2215671B3 (enExample) 1976-11-19

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