DE2361657A1 - Umlauf-zwischenspeicher - Google Patents

Umlauf-zwischenspeicher

Info

Publication number
DE2361657A1
DE2361657A1 DE2361657A DE2361657A DE2361657A1 DE 2361657 A1 DE2361657 A1 DE 2361657A1 DE 2361657 A DE2361657 A DE 2361657A DE 2361657 A DE2361657 A DE 2361657A DE 2361657 A1 DE2361657 A1 DE 2361657A1
Authority
DE
Germany
Prior art keywords
memory
index
bits
channel
character
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2361657A
Other languages
German (de)
English (en)
Inventor
Francis Roche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cable and Wireless Ltd
Original Assignee
Cable and Wireless Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cable and Wireless Ltd filed Critical Cable and Wireless Ltd
Publication of DE2361657A1 publication Critical patent/DE2361657A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Character Input (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
DE2361657A 1972-12-11 1973-12-11 Umlauf-zwischenspeicher Pending DE2361657A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5707472A GB1447627A (en) 1972-12-11 1972-12-11 Buffer stores

Publications (1)

Publication Number Publication Date
DE2361657A1 true DE2361657A1 (de) 1974-06-12

Family

ID=10478296

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2361657A Pending DE2361657A1 (de) 1972-12-11 1973-12-11 Umlauf-zwischenspeicher

Country Status (5)

Country Link
US (1) US3890600A (enExample)
DE (1) DE2361657A1 (enExample)
FR (1) FR2209979B1 (enExample)
GB (1) GB1447627A (enExample)
IT (1) IT1006678B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS537336B2 (enExample) * 1973-12-29 1978-03-16
GB2061577B (en) * 1977-08-04 1982-10-20 Honeywell Inf Systems Data transfer control in a peripheral controller
FR2601491B1 (fr) * 1986-07-10 1992-09-04 Cit Alcatel Memoire de file d'attente

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1117361A (en) * 1965-04-05 1968-06-19 Ferranti Ltd Improvements relating to information storage devices
FR1488262A (fr) * 1966-03-08 1967-07-13 Bull General Electric Système d'emmagasinage de représentations codées de caractères
FR1581412A (enExample) * 1967-10-03 1969-09-12
US3599177A (en) * 1968-09-16 1971-08-10 Bunker Ramo Character storage and display system
GB1248681A (en) * 1969-01-08 1971-10-06 Int Computers Ltd Improvements in or relating to digital electrical information processing apparatus
US3587062A (en) * 1969-09-11 1971-06-22 Bunker Ramo Read-write control system for a recirculating storage means
BE759562A (fr) * 1969-12-31 1971-04-30 Ibm Dispositif d'emmagasinage auxiliaire et methode mise en oeuvre

Also Published As

Publication number Publication date
GB1447627A (en) 1976-08-25
FR2209979B1 (enExample) 1977-03-04
IT1006678B (it) 1976-10-20
US3890600A (en) 1975-06-17
FR2209979A1 (enExample) 1974-07-05

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