DE2355095A1 - CIRCUIT ARRANGEMENT TO AVOID THE EFFECTS OF CONTACT BREADS - Google Patents

Description

BOSSE Telefonbau GmbH October 29, 1973

1000 Berlin 36

Reichenberger Str. 78/60 2355095

B-PA 05

PATENT APPLICATION

Circuit arrangement to avoid the effects of contact bounce

The invention relates to a circuit arrangement for suppressing contact bounce for use in particular in telephone systems.

Especially in telephone systems, the interconnection of mechanical contacts and electronic circuits contact bounce causes undesirable effects. In order to avoid this, there have been various so far Opportunities became known. One of those options is instead of a simple one Make or break contact to use a changeover contact, which in turn sets a flip-flop. There in many cases it is not possible to use a changeover contact, is known in other cases Solutions of the switching impulse originating from the normally open or normally closed contact before further processing by the Electronics integrated via an R-C link, resulting in pulse distortion leads, because no exact because of the bouncing

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defined switching time exists. For this, see the "TTL cookbook by TI, pages 113 and 114 pointed out. Another known solution is used more simply to evaluate the switching state Contacts Circuit arrangements which include, inter alia. contain monostable flip-flop stages. These are mono-flops triggered by the respective first edge of a switching pulse and block the arrangement for a defined time, so that pulse edges occurring during this period - z. B. by bouncing not be evaluated. This arrangement can be because of the large capacities required do not run as an integrated solid-state circuit, preferably as a so-called LSI circuit.

The object of the present invention is therefore to provide a way that the aforementioned disadvantages avoids and makes use of simple and inexpensive electronic ones that are available today Logic components of digital technology and the possibility includes the corresponding circuit to be carried out in integrated technology.

This task is according to the invention for the generic term solved according to the characterizing part of the claim.

It is then achieved that normal, mechanically operated make or break contacts for the pulse generation can be used. In addition, the impulses emitted by these are

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moderate circuit arrangement processed in such a way that this with the lowest possible pulse distortion reach the subsequent evaluation electronics and can be processed properly by them.

Two exemplary embodiments are based on the following discussed in the drawing. The drawings show in Figure 1 and 2, basic circuits and associated Time diagrams in FIGS. 3 and 4.

As can be seen from FIGS. 1 and 3, a device triggered by any mechanical contact arrives positive pulse via input 20 once to D input 24 of a dynamic flip-flop 4 and on the other hand to an input of an exclusive-OR gate 2. Since the flip-flop 4 is at "H" at its B output 28, the DDER gate 2 switches due to its activation with "H-" at its other input from “H” to “L” at its output 29. Since the C output 21 of a binary counter 1 still has “H” potential at this point in time, the AND gate switches also from "H" to "L". The binary counter controlled by the frequency fz at its input 22 is thereby activated 1 released via its set input 26 and by the first pulse of frequency fz at its C output 21 switched to "L" potential. As a result, the AND gate 3 is blocked. The following Potential change triggered by contact bouncing in the input signal, which is effective at input 20, remain

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ineffective for further switching due to the locked AND gate. This state is retained, until the binary counter 1 has run through once. After this cycle, the C output 21 of the binary counter 1 again takes "H" potential at. By this polarity change, the flip-flop 4 is corresponding to the one on his Preparation input 23, which is connected to the E input 20 of the circuit, existing switching state set, which in the present example leads to a switchover of the B output 26 from "H" to "L" leads. With a subsequent negative pulse edge The same switching sequence takes place at the E input 20, but with the difference that now the The polarity at the B output 28 of the flip-flop 4 is opposite. At the A output 25 of this circuit arrangement is the original impulse, but with almost "the same amount delayed start and End times available. Slight pulse distortions are only in this circuit arrangement still caused by the respective phase position of the counting frequency fz. By increasing this frequency and simultaneous increase in the binary counters 1, this distortion can be made as small as desired.

The second embodiment includes a similar one Arrangement in which, however, as can be seen from FIGS. 2 and 4, after the binary counter has been released the first pulse to continue counting through a delay chain is generated according to known principles. This running

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time chain contains inverters 5 to 9 as well as that
NOR gate 10. This additional circuit arrangement eliminates any phase-dependent uncertainty
eliminated for the switch-on time.

By changing the potential from "H" to "L" on
Set input 26 of binary counter 1, for example in the case of a decadic one, is not only binary counter 1
released, but by the short-term positive impulse from the runtime chain 5 to 10 of the
Binary counter 1 triggered to zero via its reset input 27. As a result, subsequent bounce pulses or pulse distortions are not blocked until the first pulse of frequency fz arrives at input 22 of binary counter 1, but rather immediately.

B -

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Claims (4)

Patent claims: Circuit arrangement for suppressing pulse distortion caused by contact bouncing, for use in particular in telephone systems, characterized in that a gate arrangement, which consists of an exclusive OR gate (2) and an AND gate [3), the function one of the usual counting or measuring frequency fz controlled binary counter [1] is released, the in turn, the AND gate C3) for all -following during the time of its cycle Blocks the pulse distortion caused by contact bouncing and which, after one pass, causes a D-flip-flop C4) switches and thus the arrangement for the following potential change is opposite Direction prepared accordingly. 2. Circuit arrangement according to claim 1, characterized in that after the release of the binary counter (1) the first counting pulse does not come from the counting frequency fz but rather from a delay chain is derived from the release potential change 3. Circuit arrangement according to claim 2, characterized in that the delay chain from the Inverters 5 to 9 and the NOR gate 10 consists. 4. Circuit arrangement according to one or more of the preceding claims, characterized 509820/0498 indicates that the binary counter (1} with a correspondingly increased number frequency fz from a multi-link counting chain. 509820/0498