DE2257845A1 - Verfahren zum herstellen von vielschichtigen leiterplatten - Google Patents

Verfahren zum herstellen von vielschichtigen leiterplatten

Info

Publication number
DE2257845A1
DE2257845A1 DE2257845A DE2257845A DE2257845A1 DE 2257845 A1 DE2257845 A1 DE 2257845A1 DE 2257845 A DE2257845 A DE 2257845A DE 2257845 A DE2257845 A DE 2257845A DE 2257845 A1 DE2257845 A1 DE 2257845A1
Authority
DE
Germany
Prior art keywords
glass
lines
panes
glass panes
another
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2257845A
Other languages
German (de)
English (en)
Inventor
Gordon Powell Baker
Dudley Augustus Chance
David Laverne Wilcox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2257845A1 publication Critical patent/DE2257845A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE2257845A 1971-12-13 1972-11-25 Verfahren zum herstellen von vielschichtigen leiterplatten Pending DE2257845A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US20733571A 1971-12-13 1971-12-13

Publications (1)

Publication Number Publication Date
DE2257845A1 true DE2257845A1 (de) 1973-06-28

Family

ID=22770099

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2257845A Pending DE2257845A1 (de) 1971-12-13 1972-11-25 Verfahren zum herstellen von vielschichtigen leiterplatten

Country Status (3)

Country Link
JP (1) JPS4865457A (enExample)
DE (1) DE2257845A1 (enExample)
FR (1) FR2163443B1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3256588A (en) * 1962-10-23 1966-06-21 Philco Corp Method of fabricating thin film r-c circuits on single substrate
US3325881A (en) * 1963-01-08 1967-06-20 Sperry Rand Corp Electrical circuit board fabrication

Also Published As

Publication number Publication date
FR2163443B1 (enExample) 1976-06-04
FR2163443A1 (enExample) 1973-07-27
JPS4865457A (enExample) 1973-09-08

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