DE2242393C2 - Verfahren zur Herstellung einer mehrschichtigen Schaltungsanordnung aus elektrisch isolierenden Schichten - Google Patents

Verfahren zur Herstellung einer mehrschichtigen Schaltungsanordnung aus elektrisch isolierenden Schichten

Info

Publication number
DE2242393C2
DE2242393C2 DE19722242393 DE2242393A DE2242393C2 DE 2242393 C2 DE2242393 C2 DE 2242393C2 DE 19722242393 DE19722242393 DE 19722242393 DE 2242393 A DE2242393 A DE 2242393A DE 2242393 C2 DE2242393 C2 DE 2242393C2
Authority
DE
Germany
Prior art keywords
layers
electrically insulating
insulating layers
circuit arrangement
multilayer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19722242393
Other languages
German (de)
English (en)
Other versions
DE2242393A1 (de
Inventor
Dexter Anthony Clinton Corners N.Y. Jeanotte
Alfred Harold Poughkeepsie N.Y. Johnson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2242393A1 publication Critical patent/DE2242393A1/de
Application granted granted Critical
Publication of DE2242393C2 publication Critical patent/DE2242393C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0272—Adaptations for fluid transport, e.g. channels, holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0379—Stacked conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE19722242393 1971-10-14 1972-08-29 Verfahren zur Herstellung einer mehrschichtigen Schaltungsanordnung aus elektrisch isolierenden Schichten Expired DE2242393C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US18941671A 1971-10-14 1971-10-14

Publications (2)

Publication Number Publication Date
DE2242393A1 DE2242393A1 (de) 1973-04-19
DE2242393C2 true DE2242393C2 (de) 1983-09-22

Family

ID=22697230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19722242393 Expired DE2242393C2 (de) 1971-10-14 1972-08-29 Verfahren zur Herstellung einer mehrschichtigen Schaltungsanordnung aus elektrisch isolierenden Schichten

Country Status (4)

Country Link
JP (1) JPS5517519B2 (enExample)
DE (1) DE2242393C2 (enExample)
FR (1) FR2156408B1 (enExample)
GB (1) GB1363171A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3108546A1 (de) * 1981-03-06 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Durchkontaktierung fuer mehrlagen-leiterplatten

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3141238A (en) * 1960-11-22 1964-07-21 Jr George G Harman Method of low temperature bonding for subsequent high temperature use
US3193789A (en) * 1962-08-01 1965-07-06 Sperry Rand Corp Electrical circuitry
US3233034A (en) * 1964-10-26 1966-02-01 Dimitry G Grabbe Diffusion bonded printed circuit terminal structure

Also Published As

Publication number Publication date
GB1363171A (en) 1974-08-14
FR2156408A1 (enExample) 1973-05-25
JPS5517519B2 (enExample) 1980-05-12
JPS4846864A (enExample) 1973-07-04
DE2242393A1 (de) 1973-04-19
FR2156408B1 (enExample) 1975-09-12

Similar Documents

Publication Publication Date Title
DE69207520T2 (de) Elektrische Leiterplattenbaugruppe und Herstellungsverfahren für eine elektrische Leiterplattenbaugruppe
EP0004899B1 (de) Verfahren zur Herstellung elektrisch leitender und schwingungssicherer Verbindungen zwischen gedruckten Rückwandverdrahtungen von Leiterplatten und Kontaktfedern einer Federleiste, sowie hierfür geeignete Federleiste
DE3788455T2 (de) Bandstruktur für automatische Bandmontage, Mehrschichtpackung und universelle Chipverbindung.
DE19928788A1 (de) Elektronische Keramikkomponente
DE4192038C2 (de) Herstellungsverfahren für bedruckte Schaltungsplatinen, bei dem sowohl Wellenlöten als auch das Einpressen von Bauteilen ermöglicht wird
DE2852753B2 (de) Verfahren zum Befestigen von Bauelementen mit flächigen Anschlußkontakten auf einer Leiterplatte
DE69723801T2 (de) Herstellungsverfahren einer Kontaktgitter-Halbleiterpackung
DE69704678T2 (de) Verfahren zum herstellen einer leiterplatteranordnung mit zinn/bleischicht
DE4026972A1 (de) Loetverbinder und verfahren zur herstellung einer elektrischen schaltung mit diesem loetverbinder
DE102018116410A1 (de) Verfahren zur Herstellung einer hochtemperaturfesten bleifreien Lotverbindung und hochtemperaturfeste bleifreie Lotverbindung
DE68906160T2 (de) Gedruckte Schaltungsplatte.
DE10123684A1 (de) Leiterplatte mit einer darauf aufgebrachten Kontakthülse
DE102020100364B4 (de) Leistungselektronische Baugruppe mit einem Substrat, einer Hülse und einem Kontaktstift und Verfahren zur Herstellung einer solchen Baugruppe
EP1606982A2 (de) Verfahren und vorrichtung zur elektrischen und mechanischen verbindung zweier leiterplatten
DE3853673T2 (de) Automatische Bandmontage-Packung.
WO2016000909A1 (de) Leiterplattenverbindungselement
DE68914214T2 (de) Zusammenbau- und Packungsverfahren eines Sensorelementes.
WO2006013145A1 (de) Leiterplatte mit smd-bauteilen und mindestens einem bedrahteten bauteil sowie ein verfahren zum bestücken, befestigen und elektrischen kontaktieren der bauteile
DE1292755B (de) Verfahren zum serienmaessigen Sockeln und Gehaeuseeinbau von Halbleiterbauelementen
DE102012112546A1 (de) Verfahren zur Herstellung von mischbestückten Leiterplatten
DE1465736A1 (de) Verfahren zur Herstellung von Funktionsblocks,insbesondere fuer datenverarbeitende Anlagen
DE2242393A1 (de) Mehrschichtige anordnung und verfahren zur herstellung derselben
DE19512272C2 (de) Verfahren zur Herstellung einer mehrschichtigen Leiterplatte für ein Chassis eines unterhaltungselektronischen Gerätes und Leiterplatte hergestellt nach diesem Verfahren
DE19540570A1 (de) Leiterplatte und Verfahren zu ihrer Herstellung
DE4337920A1 (de) Verfahren und Anordnung zur Erzeugung eines permanenten elektrischen Druckkontaktes

Legal Events

Date Code Title Description
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: NEULAND, J., DIPL.-ING., PAT.-ASS., 7030 BOEBLINGE

8125 Change of the main classification

Ipc: H05K 3/40

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee