DE2212501C2 - Einrichtung zur Übertragung asynchroner, digitaler Signale - Google Patents

Einrichtung zur Übertragung asynchroner, digitaler Signale

Info

Publication number
DE2212501C2
DE2212501C2 DE2212501A DE2212501A DE2212501C2 DE 2212501 C2 DE2212501 C2 DE 2212501C2 DE 2212501 A DE2212501 A DE 2212501A DE 2212501 A DE2212501 A DE 2212501A DE 2212501 C2 DE2212501 C2 DE 2212501C2
Authority
DE
Germany
Prior art keywords
memory
flip
output
data
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2212501A
Other languages
German (de)
English (en)
Other versions
DE2212501A1 (de
Inventor
Reinhard Kurt Glendora Calif. Kronies
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of DE2212501A1 publication Critical patent/DE2212501A1/de
Application granted granted Critical
Publication of DE2212501C2 publication Critical patent/DE2212501C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Cable Accessories (AREA)
  • Silicon Polymers (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
DE2212501A 1971-03-15 1972-03-15 Einrichtung zur Übertragung asynchroner, digitaler Signale Expired DE2212501C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12395971A 1971-03-15 1971-03-15

Publications (2)

Publication Number Publication Date
DE2212501A1 DE2212501A1 (de) 1973-02-08
DE2212501C2 true DE2212501C2 (de) 1983-07-14

Family

ID=22411936

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2212501A Expired DE2212501C2 (de) 1971-03-15 1972-03-15 Einrichtung zur Übertragung asynchroner, digitaler Signale

Country Status (6)

Country Link
US (1) US3742253A (enExample)
JP (1) JPS549453B1 (enExample)
BE (1) BE780712A (enExample)
DE (1) DE2212501C2 (enExample)
FR (1) FR2132016B1 (enExample)
GB (2) GB1366401A (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4449064A (en) * 1981-04-02 1984-05-15 Motorola, Inc. Three state output circuit
US4814638A (en) * 1987-06-08 1989-03-21 Grumman Aerospace Corporation High speed digital driver with selectable level shifter
US7133972B2 (en) * 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7200024B2 (en) * 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7260685B2 (en) 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7428644B2 (en) 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7133991B2 (en) 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7788451B2 (en) * 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7412574B2 (en) 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US7447240B2 (en) * 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7363419B2 (en) 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL289344A (enExample) * 1962-02-24
US3136901A (en) * 1962-03-01 1964-06-09 Rca Corp Information handling apparatus
US3509381A (en) * 1967-01-11 1970-04-28 Honeywell Inc Multivibrator circuit including output buffer means and logic means
US3484701A (en) * 1967-03-31 1969-12-16 Bell Telephone Labor Inc Asynchronous sequential switching circuit using a single feedback delay element
GB1184568A (en) * 1967-05-02 1970-03-18 Mullard Ltd Improvements in or relating to Bistable Circuits.
US3575608A (en) * 1969-07-29 1971-04-20 Rca Corp Circuit for detecting a change in voltage level in either sense

Also Published As

Publication number Publication date
US3742253A (en) 1973-06-26
FR2132016A1 (enExample) 1972-11-17
GB1366401A (en) 1974-09-11
BE780712A (fr) 1972-07-03
FR2132016B1 (enExample) 1974-12-06
GB1366403A (en) 1974-09-11
DE2212501A1 (de) 1973-02-08
JPS549453B1 (enExample) 1979-04-24

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Legal Events

Date Code Title Description
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: EISENFUEHR, G., DIPL.-ING. SPEISER, D., DIPL.-ING.

8126 Change of the secondary classification

Free format text: G11C 7/00 G06F 3/04 H03K 19/20 G11C 19/00

8181 Inventor (new situation)

Free format text: KRONIES, REINHARD KURT, GLENDORA, CALIF., US

D2 Grant after examination
8364 No opposition during term of opposition
8330 Complete disclaimer